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[AMD Official Use Only]<br>
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Why not move changes into<font size="2"><span style="font-size:11pt"> hw_fini?</span></font><br>
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<p style="margin-top: 0px; margin-bottom: 0px;">Best Regards!</p>
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<p style="margin-top: 0px; margin-bottom: 0px;">James Zhu<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Evan Quan <evan.quan@amd.com><br>
<b>Sent:</b> Wednesday, August 18, 2021 11:08 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Lazar, Lijo <Lijo.Lazar@amd.com>; Quan, Evan <Evan.Quan@amd.com>; Pan, Xinhui <Xinhui.Pan@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: add missing cleanups for Polaris12 UVD/VCE on suspend</font>
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<div class="PlainText">Perform proper cleanups on UVD/VCE suspend: powergate enablement,<br>
clockgating enablement and dpm disablement. This can fix some hangs<br>
observed on suspending when UVD/VCE still using(e.g. issue<br>
"pm-suspend" when video is still playing).<br>
<br>
Change-Id: I36f39d9731e0a9638b52d5d92558b0ee9c23a9ed<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
Signed-off-by: xinhui pan <xinhui.pan@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 24 ++++++++++++++++++++++++<br>
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 23 +++++++++++++++++++++++<br>
2 files changed, 47 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c<br>
index 4eebf973a065..d0fc6ec18c29 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c<br>
@@ -554,6 +554,30 @@ static int uvd_v6_0_suspend(void *handle)<br>
int r;<br>
struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
<br>
+ /*<br>
+ * Proper cleanups before halting the HW engine:<br>
+ * - cancel the delayed idle work<br>
+ * - enable powergating<br>
+ * - enable clockgating<br>
+ * - disable dpm<br>
+ *<br>
+ * TODO: to align with the VCN implementation, move the<br>
+ * jobs for clockgating/powergating/dpm setting to<br>
+ * ->set_powergating_state().<br>
+ */<br>
+ cancel_delayed_work_sync(&adev->uvd.idle_work);<br>
+<br>
+ if (adev->pm.dpm_enabled) {<br>
+ amdgpu_dpm_enable_uvd(adev, false);<br>
+ } else {<br>
+ amdgpu_asic_set_uvd_clocks(adev, 0, 0);<br>
+ /* shutdown the UVD block */<br>
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD,<br>
+ AMD_PG_STATE_GATE);<br>
+ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD,<br>
+ AMD_CG_STATE_GATE);<br>
+ }<br>
+<br>
r = uvd_v6_0_hw_fini(adev);<br>
if (r)<br>
return r;<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c<br>
index 6d9108fa22e0..a594ade5d30a 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c<br>
@@ -503,6 +503,29 @@ static int vce_v3_0_suspend(void *handle)<br>
int r;<br>
struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
<br>
+ /*<br>
+ * Proper cleanups before halting the HW engine:<br>
+ * - cancel the delayed idle work<br>
+ * - enable powergating<br>
+ * - enable clockgating<br>
+ * - disable dpm<br>
+ *<br>
+ * TODO: to align with the VCN implementation, move the<br>
+ * jobs for clockgating/powergating/dpm setting to<br>
+ * ->set_powergating_state().<br>
+ */<br>
+ cancel_delayed_work_sync(&adev->vce.idle_work);<br>
+<br>
+ if (adev->pm.dpm_enabled) {<br>
+ amdgpu_dpm_enable_vce(adev, false);<br>
+ } else {<br>
+ amdgpu_asic_set_vce_clocks(adev, 0, 0);<br>
+ amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,<br>
+ AMD_PG_STATE_GATE);<br>
+ amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,<br>
+ AMD_CG_STATE_GATE);<br>
+ }<br>
+<br>
r = vce_v3_0_hw_fini(adev);<br>
if (r)<br>
return r;<br>
-- <br>
2.29.0<br>
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