<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"> </head> <body> Yes, correct but the key point is I want the same handling for old and new UVD blocks to be the same. This makes it more likely that the code keeps working on all hardware generations when we change something. See those old hardware is rare to get these days and I don't want to risk any bug report from end users when we didn't tested that well on SI/CIK. Christian. <div class="moz-cite-prefix">Am 09.09.21 um 10:11 schrieb Pan, Xinhui: </div> <blockquote type="cite" cite="mid:DM4PR12MB5165F781E6DA18852A01640C87D59@DM4PR12MB5165.namprd12.prod.outlook.com"> <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"> [AMD Official Use Only] <div> <div dir="auto" style="direction: ltr; margin: 0px; padding: 0px; font-family: sans-serif; font-size: 11pt; color: black; text-align: left;"> well, If IB test fails because we use gtt domain or</div> <div dir="auto" style="direction: ltr; margin: 0px; padding: 0px; font-family: sans-serif; font-size: 11pt; color: black; text-align: left;"> the above 256MB vram. Then the failure is expected. </div> <div dir="auto" style="direction: ltr; margin: 0px; padding: 0px; font-family: sans-serif; font-size: 11pt; color: black; text-align: left;"> Doesn't IB test exist to detect such issue?</div> <div id="id-6c97172e-0116-45da-8423-7906d63f733c" class="ms-outlook-mobile-reference-message"> <div style="font-family: sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> </div> <hr style="display:inline-block;width:98%" tabindex="-1"> <div id="divRplyFwdMsg">发件人: Koenig, Christian <a class="moz-txt-link-rfc2396E" href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a> 发送时间: 2021年9月9日星期四 15:16 收件人: Pan, Xinhui; <a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> 抄送: Deucher, Alexander 主题: Re: [PATCH 2/2] drm/amdgpu: alloc IB extra msg from IB pool </div> <meta name="Generator" content="Microsoft Exchange Server">  <style>.EmailQuote { margin-left: 1pt; padding-left: 4pt; border-left: #800000 2px solid; }</style> <div class="PlainText">Am 09.09.21 um 07:55 schrieb Pan, Xinhui: > [AMD Official Use Only] > > There is one dedicated IB pool for IB test. So lets use it for extra msg > too. > > For UVD on older HW, use one reserved BO at specific range. > > Signed-off-by: xinhui pan <a class="moz-txt-link-rfc2396E" href="mailto:xinhui.pan@amd.com"><xinhui.pan@amd.com></a> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 173 +++++++++++++++--------- > drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 18 +-- > drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 99 ++++++-------- > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 28 ++-- > drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 28 ++-- > 6 files changed, 185 insertions(+), 162 deletions(-) Please split that up into one patch for UVD, one for VCE and a third for VCN. > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c > index d451c359606a..733cfc848c6c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c > @@ -299,8 +299,36 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) > } > > /* from uvd v5.0 HW addressing capacity increased to 64 bits */ > - if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) > + if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) { > adev->uvd.address_64_bit = true; Yeah, that's exactly what I'm trying to avoid. We should use the BO approach both for old and new UVD blocks, just making sure that we place it correctly for the old ones. This way we have much lower chance of breaking the old stuff. Thanks, Christian. > + } else { > + struct amdgpu_bo *bo = NULL; > + void *addr; > + > + r = amdgpu_bo_create_reserved(adev, PAGE_SIZE, PAGE_SIZE, > + AMDGPU_GEM_DOMAIN_VRAM, > + &bo, NULL, &addr); > + if (r) > + return r; > + amdgpu_bo_kunmap(bo); > + amdgpu_bo_unpin(bo); > + r = amdgpu_bo_pin_restricted(bo, AMDGPU_GEM_DOMAIN_VRAM, > + 0, 256 << 20); > + if (r) { > + amdgpu_bo_unreserve(bo); > + amdgpu_bo_unref(&bo); > + return r; > + } > + r = amdgpu_bo_kmap(bo, &addr); > + if (r) { > + amdgpu_bo_unpin(bo); > + amdgpu_bo_unreserve(bo); > + amdgpu_bo_unref(&bo); > + return r; > + } > + adev->uvd.ib_bo = bo; > + amdgpu_bo_unreserve(bo); > + } > > switch (adev->asic_type) { > case CHIP_TONGA: > @@ -342,6 +370,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) > for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) > amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); > } > + amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, NULL); > release_firmware(adev->uvd.fw); > > return 0; > @@ -1066,7 +1095,7 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) > return 0; > } > > -static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, > +static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, uint64_t addr, > bool direct, struct dma_fence **fence) > { > struct amdgpu_device *adev = ring->adev; > @@ -1074,29 +1103,15 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, > struct amdgpu_job *job; > struct amdgpu_ib *ib; > uint32_t data[4]; > - uint64_t addr; > long r; > int i; > unsigned offset_idx = 0; > unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; > > - amdgpu_bo_kunmap(bo); > - amdgpu_bo_unpin(bo); > - > - if (!ring->adev->uvd.address_64_bit) { > - struct ttm_operation_ctx ctx = { true, false }; > - > - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); > - amdgpu_uvd_force_into_uvd_segment(bo); > - r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); > - if (r) > - goto err; > - } > - > r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT : > AMDGPU_IB_POOL_DELAYED, &job); > if (r) > - goto err; > + return r; > > if (adev->asic_type >= CHIP_VEGA10) { > offset_idx = 1 + ring->me; > @@ -1110,7 +1125,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, > data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > ib->ptr[0] = data[0]; > ib->ptr[1] = addr; > ib->ptr[2] = data[1]; > @@ -1123,33 +1137,13 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, > } > ib->length_dw = 16; > > - if (direct) { > - r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false, > - msecs_to_jiffies(10)); > - if (r == 0) > - r = -ETIMEDOUT; > - if (r < 0) > - goto err_free; > - > + if (direct) > r = amdgpu_job_submit_direct(job, ring, &f); > - if (r) > - goto err_free; > - } else { > - r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, > - AMDGPU_SYNC_ALWAYS, > - AMDGPU_FENCE_OWNER_UNDEFINED); > - if (r) > - goto err_free; > - > + else > r = amdgpu_job_submit(job, &adev->uvd.entity, > - AMDGPU_FENCE_OWNER_UNDEFINED, &f); > - if (r) > - goto err_free; > - } > - > - amdgpu_bo_fence(bo, f, false); > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_unref(&bo); > + AMDGPU_FENCE_OWNER_UNDEFINED, &f); > + if (r) > + goto err_free; > > if (fence) > *fence = dma_fence_get(f); > @@ -1159,10 +1153,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, > > err_free: > amdgpu_job_free(job); > - > -err: > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_unref(&bo); > return r; > } > > @@ -1173,16 +1163,31 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > struct dma_fence **fence) > { > struct amdgpu_device *adev = ring->adev; > - struct amdgpu_bo *bo = NULL; > + struct amdgpu_bo *bo = adev->uvd.ib_bo; > + struct dma_fence *f = NULL; > + struct amdgpu_ib ib; > uint32_t *msg; > int r, i; > > - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_GTT, > - &bo, NULL, (void **)&msg); > - if (r) > - return r; > - > + if (bo) { > + r = ttm_bo_reserve(&bo->tbo, true, true, NULL); > + if (r) > + return r; > + r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false, > + msecs_to_jiffies(10)); > + if (r == 0) > + r = -ETIMEDOUT; > + if (r < 0) > + goto err; > + ib.gpu_addr = amdgpu_bo_gpu_offset(bo); > + msg = amdgpu_bo_kptr(bo); > + } else { > + memset(&ib, 0, sizeof(ib)); > + r = amdgpu_ib_get(adev, NULL, PAGE_SIZE, > + AMDGPU_IB_POOL_DIRECT, > + &ib); > + msg = ib.ptr; > + } > /* stitch together an UVD create msg */ > msg[0] = cpu_to_le32(0x00000de4); > msg[1] = cpu_to_le32(0x00000000); > @@ -1198,23 +1203,52 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > for (i = 11; i < 1024; ++i) > msg[i] = cpu_to_le32(0x0); > > - return amdgpu_uvd_send_msg(ring, bo, true, fence); > + r = amdgpu_uvd_send_msg(ring, ib.gpu_addr, true, &f); > + if (r) > + goto err; > + if (bo) > + amdgpu_bo_fence(bo, f, false); > + if (fence) > + *fence = dma_fence_get(f); > +err: > + if (bo) > + amdgpu_bo_unreserve(bo); > + else > + amdgpu_ib_free(adev, &ib, f); > + dma_fence_put(f); > + return r; > } > > int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, > bool direct, struct dma_fence **fence) > { > struct amdgpu_device *adev = ring->adev; > - struct amdgpu_bo *bo = NULL; > + struct amdgpu_bo *bo = adev->uvd.ib_bo; > + struct dma_fence *f = NULL; > + struct amdgpu_ib ib; > uint32_t *msg; > int r, i; > > - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_GTT, > - &bo, NULL, (void **)&msg); > - if (r) > - return r; > - > + if (bo) { > + r = ttm_bo_reserve(&bo->tbo, true, true, NULL); > + if (r) > + return r; > + r = dma_resv_wait_timeout(bo->tbo.base.resv, true, false, > + msecs_to_jiffies(10)); > + if (r == 0) > + r = -ETIMEDOUT; > + if (r < 0) > + goto err; > + ib.gpu_addr = amdgpu_bo_gpu_offset(bo); > + msg = amdgpu_bo_kptr(bo); > + } else { > + memset(&ib, 0, sizeof(ib)); > + r = amdgpu_ib_get(adev, NULL, PAGE_SIZE, > + direct ? > + AMDGPU_IB_POOL_DIRECT : AMDGPU_IB_POOL_DELAYED, > + &ib); > + msg = ib.ptr; > + } > /* stitch together an UVD destroy msg */ > msg[0] = cpu_to_le32(0x00000de4); > msg[1] = cpu_to_le32(0x00000002); > @@ -1223,7 +1257,20 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, > for (i = 4; i < 1024; ++i) > msg[i] = cpu_to_le32(0x0); > > - return amdgpu_uvd_send_msg(ring, bo, direct, fence); > + r = amdgpu_uvd_send_msg(ring, ib.gpu_addr, true, &f); > + if (r) > + goto err; > + if (bo) > + amdgpu_bo_fence(bo, f, false); > + if (fence) > + *fence = dma_fence_get(f); > +err: > + if (bo) > + amdgpu_bo_unreserve(bo); > + else > + amdgpu_ib_free(adev, &ib, f); > + dma_fence_put(f); > + return r; > } > > static void amdgpu_uvd_idle_work_handler(struct work_struct *work) > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h > index edbb8194ee81..76ac9699885d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h > @@ -68,6 +68,7 @@ struct amdgpu_uvd { > /* store image width to adjust nb memory state */ > unsigned decode_image_width; > uint32_t keyselect; > + struct amdgpu_bo *ib_bo; > }; > > int amdgpu_uvd_sw_init(struct amdgpu_device *adev); > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c > index e9fdf49d69e8..45d98694db18 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c > @@ -82,7 +82,6 @@ MODULE_FIRMWARE(FIRMWARE_VEGA20); > > static void amdgpu_vce_idle_work_handler(struct work_struct *work); > static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo *bo, > struct dma_fence **fence); > static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, > bool direct, struct dma_fence **fence); > @@ -441,7 +440,6 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp) > * Open up a stream for HW test > */ > static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo *bo, > struct dma_fence **fence) > { > const unsigned ib_size_dw = 1024; > @@ -451,14 +449,13 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > uint64_t addr; > int i, r; > > - r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, > + r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4 + PAGE_SIZE, > AMDGPU_IB_POOL_DIRECT, &job); > if (r) > return r; > > ib = &job->ibs[0]; > - > - addr = amdgpu_bo_gpu_offset(bo); > + addr = ib->gpu_addr + ib_size_dw * 4; > > /* stitch together an VCE create msg */ > ib->length_dw = 0; > @@ -1134,20 +1131,13 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring) > int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) > { > struct dma_fence *fence = NULL; > - struct amdgpu_bo *bo = NULL; > long r; > > /* skip vce ring1/2 ib test for now, since it's not reliable */ > if (ring != &ring->adev->vce.ring[0]) > return 0; > > - r = amdgpu_bo_create_reserved(ring->adev, 512, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_VRAM, > - &bo, NULL, NULL); > - if (r) > - return r; > - > - r = amdgpu_vce_get_create_msg(ring, 1, bo, NULL); > + r = amdgpu_vce_get_create_msg(ring, 1, NULL); > if (r) > goto error; > > @@ -1163,8 +1153,6 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout) > > error: > dma_fence_put(fence); > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_free_kernel(&bo, NULL, NULL); > return r; > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > index 561296a85b43..b60d5f01fdae 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c > @@ -541,15 +541,14 @@ int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring) > } > > static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, > - struct amdgpu_bo *bo, > - struct dma_fence **fence) > + struct amdgpu_ib *ib_msg, > + struct dma_fence **fence) > { > struct amdgpu_device *adev = ring->adev; > struct dma_fence *f = NULL; > struct amdgpu_job *job; > struct amdgpu_ib *ib; > - uint64_t addr; > - void *msg = NULL; > + uint64_t addr = ib_msg->gpu_addr; > int i, r; > > r = amdgpu_job_alloc_with_ib(adev, 64, > @@ -558,8 +557,6 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, > goto err; > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > - msg = amdgpu_bo_kptr(bo); > ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0); > ib->ptr[1] = addr; > ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0); > @@ -576,9 +573,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, > if (r) > goto err_free; > > - amdgpu_bo_fence(bo, f, false); > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); > + amdgpu_ib_free(adev, ib_msg, f); > > if (fence) > *fence = dma_fence_get(f); > @@ -588,27 +583,26 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring, > > err_free: > amdgpu_job_free(job); > - > err: > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg); > + amdgpu_ib_free(adev, ib_msg, f); > return r; > } > > static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo **bo) > + struct amdgpu_ib *ib) > { > struct amdgpu_device *adev = ring->adev; > uint32_t *msg; > int r, i; > > - *bo = NULL; > - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_VRAM, > - bo, NULL, (void **)&msg); > + memset(ib, 0, sizeof(*ib)); > + r = amdgpu_ib_get(adev, NULL, PAGE_SIZE, > + AMDGPU_IB_POOL_DIRECT, > + ib); > if (r) > return r; > > + msg = ib->ptr; > msg[0] = cpu_to_le32(0x00000028); > msg[1] = cpu_to_le32(0x00000038); > msg[2] = cpu_to_le32(0x00000001); > @@ -630,19 +624,20 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand > } > > static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo **bo) > + struct amdgpu_ib *ib) > { > struct amdgpu_device *adev = ring->adev; > uint32_t *msg; > int r, i; > > - *bo = NULL; > - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_VRAM, > - bo, NULL, (void **)&msg); > + memset(ib, 0, sizeof(*ib)); > + r = amdgpu_ib_get(adev, NULL, PAGE_SIZE, > + AMDGPU_IB_POOL_DIRECT, > + ib); > if (r) > return r; > > + msg = ib->ptr; > msg[0] = cpu_to_le32(0x00000028); > msg[1] = cpu_to_le32(0x00000018); > msg[2] = cpu_to_le32(0x00000000); > @@ -658,21 +653,21 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han > int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) > { > struct dma_fence *fence = NULL; > - struct amdgpu_bo *bo; > + struct amdgpu_ib ib; > long r; > > - r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo); > + r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); > if (r) > goto error; > > - r = amdgpu_vcn_dec_send_msg(ring, bo, NULL); > + r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL); > if (r) > goto error; > - r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo); > + r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); > if (r) > goto error; > > - r = amdgpu_vcn_dec_send_msg(ring, bo, &fence); > + r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence); > if (r) > goto error; > > @@ -688,8 +683,8 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout) > } > > static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, > - struct amdgpu_bo *bo, > - struct dma_fence **fence) > + struct amdgpu_ib *ib_msg, > + struct dma_fence **fence) > { > struct amdgpu_vcn_decode_buffer *decode_buffer = NULL; > const unsigned int ib_size_dw = 64; > @@ -697,7 +692,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, > struct dma_fence *f = NULL; > struct amdgpu_job *job; > struct amdgpu_ib *ib; > - uint64_t addr; > + uint64_t addr = ib_msg->gpu_addr; > int i, r; > > r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4, > @@ -706,7 +701,6 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, > goto err; > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > ib->length_dw = 0; > > ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8; > @@ -726,9 +720,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, > if (r) > goto err_free; > > - amdgpu_bo_fence(bo, f, false); > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_unref(&bo); > + amdgpu_ib_free(adev, ib_msg, f); > > if (fence) > *fence = dma_fence_get(f); > @@ -738,31 +730,29 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring, > > err_free: > amdgpu_job_free(job); > - > err: > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_unref(&bo); > + amdgpu_ib_free(adev, ib_msg, f); > return r; > } > > int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout) > { > struct dma_fence *fence = NULL; > - struct amdgpu_bo *bo; > + struct amdgpu_ib ib; > long r; > > - r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo); > + r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib); > if (r) > goto error; > > - r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL); > + r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL); > if (r) > goto error; > - r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo); > + r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib); > if (r) > goto error; > > - r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence); > + r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence); > if (r) > goto error; > > @@ -809,7 +799,7 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring) > } > > static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo *bo, > + struct amdgpu_ib *ib_msg, > struct dma_fence **fence) > { > const unsigned ib_size_dw = 16; > @@ -825,7 +815,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand > return r; > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > + addr = ib_msg->gpu_addr; > > ib->length_dw = 0; > ib->ptr[ib->length_dw++] = 0x00000018; > @@ -863,7 +853,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand > } > > static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo *bo, > + struct amdgpu_ib *ib_msg, > struct dma_fence **fence) > { > const unsigned ib_size_dw = 16; > @@ -879,7 +869,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han > return r; > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > + addr = ib_msg->gpu_addr; > > ib->length_dw = 0; > ib->ptr[ib->length_dw++] = 0x00000018; > @@ -918,21 +908,23 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han > > int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) > { > + struct amdgpu_device *adev = ring->adev; > struct dma_fence *fence = NULL; > - struct amdgpu_bo *bo = NULL; > + struct amdgpu_ib ib; > long r; > > - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_VRAM, > - &bo, NULL, NULL); > + memset(&ib, 0, sizeof(ib)); > + r = amdgpu_ib_get(adev, NULL, 128 << 10, > + AMDGPU_IB_POOL_DIRECT, > + &ib); > if (r) > return r; > > - r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL); > + r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL); > if (r) > goto error; > > - r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence); > + r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence); > if (r) > goto error; > > @@ -943,9 +935,8 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) > r = 0; > > error: > + amdgpu_ib_free(adev, &ib, fence); > dma_fence_put(fence); > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_free_kernel(&bo, NULL, NULL); > > return r; > } > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index bc571833632e..98442462135c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -206,14 +206,14 @@ static int uvd_v6_0_enc_ring_test_ring(struct amdgpu_ring *ring) > * Open up a stream for HW test > */ > static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo *bo, > + struct amdgpu_ib *ib_msg, > struct dma_fence **fence) > { > const unsigned ib_size_dw = 16; > struct amdgpu_job *job; > struct amdgpu_ib *ib; > struct dma_fence *f = NULL; > - uint64_t addr; > + uint64_t addr = ib_msg->gpu_addr; > int i, r; > > r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, > @@ -222,7 +222,6 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle > return r; > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > > ib->length_dw = 0; > ib->ptr[ib->length_dw++] = 0x00000018; > @@ -270,14 +269,14 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle > */ > static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, > uint32_t handle, > - struct amdgpu_bo *bo, > + struct amdgpu_ib *ib_msg, > struct dma_fence **fence) > { > const unsigned ib_size_dw = 16; > struct amdgpu_job *job; > struct amdgpu_ib *ib; > struct dma_fence *f = NULL; > - uint64_t addr; > + uint64_t addr = ib_msg->gpu_addr; > int i, r; > > r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, > @@ -286,7 +285,6 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, > return r; > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > > ib->length_dw = 0; > ib->ptr[ib->length_dw++] = 0x00000018; > @@ -331,21 +329,23 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring, > */ > static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) > { > + struct amdgpu_device *adev = ring->adev; > struct dma_fence *fence = NULL; > - struct amdgpu_bo *bo = NULL; > + struct amdgpu_ib ib; > long r; > > - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_VRAM, > - &bo, NULL, NULL); > + memset(&ib, 0, sizeof(ib)); > + r = amdgpu_ib_get(adev, NULL, 128 << 10, > + AMDGPU_IB_POOL_DIRECT, > + &ib); > if (r) > return r; > > - r = uvd_v6_0_enc_get_create_msg(ring, 1, bo, NULL); > + r = uvd_v6_0_enc_get_create_msg(ring, 1, &ib, NULL); > if (r) > goto error; > > - r = uvd_v6_0_enc_get_destroy_msg(ring, 1, bo, &fence); > + r = uvd_v6_0_enc_get_destroy_msg(ring, 1, &ib, &fence); > if (r) > goto error; > > @@ -356,10 +356,8 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) > r = 0; > > error: > + amdgpu_ib_free(adev, &ib, fence); > dma_fence_put(fence); > - amdgpu_bo_unpin(bo); > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_unref(&bo); > return r; > } > > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > index b6e82d75561f..3440ef554f99 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > @@ -213,14 +213,14 @@ static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring) > * Open up a stream for HW test > */ > static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo *bo, > + struct amdgpu_ib *ib_msg, > struct dma_fence **fence) > { > const unsigned ib_size_dw = 16; > struct amdgpu_job *job; > struct amdgpu_ib *ib; > struct dma_fence *f = NULL; > - uint64_t addr; > + uint64_t addr = ib_msg->gpu_addr; > int i, r; > > r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, > @@ -229,7 +229,6 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle > return r; > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > > ib->length_dw = 0; > ib->ptr[ib->length_dw++] = 0x00000018; > @@ -276,14 +275,14 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle > * Close up a stream for HW test or if userspace failed to do so > */ > static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, > - struct amdgpu_bo *bo, > + struct amdgpu_ib *ib_msg, > struct dma_fence **fence) > { > const unsigned ib_size_dw = 16; > struct amdgpu_job *job; > struct amdgpu_ib *ib; > struct dma_fence *f = NULL; > - uint64_t addr; > + uint64_t addr = ib_msg->gpu_addr; > int i, r; > > r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, > @@ -292,7 +291,6 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl > return r; > > ib = &job->ibs[0]; > - addr = amdgpu_bo_gpu_offset(bo); > > ib->length_dw = 0; > ib->ptr[ib->length_dw++] = 0x00000018; > @@ -337,21 +335,23 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl > */ > static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) > { > + struct amdgpu_device *adev = ring->adev; > struct dma_fence *fence = NULL; > - struct amdgpu_bo *bo = NULL; > + struct amdgpu_ib ib; > long r; > > - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE, > - AMDGPU_GEM_DOMAIN_VRAM, > - &bo, NULL, NULL); > + memset(&ib, 0, sizeof(ib)); > + r = amdgpu_ib_get(adev, NULL, 128 << 10, > + AMDGPU_IB_POOL_DIRECT, > + &ib); > if (r) > return r; > > - r = uvd_v7_0_enc_get_create_msg(ring, 1, bo, NULL); > + r = uvd_v7_0_enc_get_create_msg(ring, 1, &ib, NULL); > if (r) > goto error; > > - r = uvd_v7_0_enc_get_destroy_msg(ring, 1, bo, &fence); > + r = uvd_v7_0_enc_get_destroy_msg(ring, 1, &ib, &fence); > if (r) > goto error; > > @@ -362,10 +362,8 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) > r = 0; > > error: > + amdgpu_ib_free(adev, &ib, fence); > dma_fence_put(fence); > - amdgpu_bo_unpin(bo); > - amdgpu_bo_unreserve(bo); > - amdgpu_bo_unref(&bo); > return r; > } > > -- > 2.25.1 > </div> </div> </div> </blockquote> </body> </html>