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[AMD Official Use Only]<br>
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That is not how the register works. The *16 has nothing to do with cu counts. This is to address the upper and lower 16 bits in the register as each half of the register programs a separate SH.</div>
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<div id="divRplyFwdMsg"><strong>From:</strong> Huang, Ray <Ray.Huang@amd.com><br>
<strong>Sent:</strong> Thursday, September 23, 2021, 12:42 AM<br>
<strong>To:</strong> amd-gfx@lists.freedesktop.org<br>
<strong>Cc:</strong> Kuehling, Felix; Keely, Sean; Deucher, Alexander; Yu, Lang; Gong, Curry; Huang, Ray<br>
<strong>Subject:</strong> [PATCH 1/2] drm/amdgpu: fix to use real compute unit number for shader array mask<br>
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<div class="PlainText">We should use the real compute unit number for shader array mask. Some<br>
asic doesn't have 16 compute units per shader array.<br>
<br>
Signed-off-by: Huang Rui <ray.huang@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c | 4 ++--<br>
1 file changed, 2 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c<br>
index c021519af810..0891c937f4da 100644<br>
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c<br>
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.c<br>
@@ -159,12 +159,12 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,<br>
se_mask[i] = 0;<br>
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i = 0;<br>
- for (cu = 0; cu < 16; cu++) {<br>
+ for (cu = 0; cu < cu_info.num_cu_per_sh; cu++) {<br>
for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {<br>
for (se = 0; se < cu_info.num_shader_engines; se++) {<br>
if (cu_per_sh[se][sh] > cu) {<br>
if (cu_mask[i / 32] & (1 << (i % 32)))<br>
- se_mask[se] |= 1 << (cu + sh * 16);<br>
+ se_mask[se] |= 1 << (cu + sh * cu_info.num_cu_per_sh);<br>
i++;<br>
if (i == cu_mask_count)<br>
return;<br>
-- <br>
2.25.1<br>
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