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[AMD Official Use Only]<br>
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Reviewed-by:<span style="color:#c0c0c0"> </span>James<span style="color:#c0c0c0">
</span>Zhu<span style="color:#c0c0c0"> </span><James.Zhu@amd.com><span style="color:#c0c0c0">
</span><span style="color:#ff9d04">for</span><span style="color:#c0c0c0"> </span>
the<span style="color:#c0c0c0"> </span>series.<br>
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<p style="margin-top: 0px; margin-bottom: 0px;">James Zhu<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Alex Deucher <alexander.deucher@amd.com><br>
<b>Sent:</b> Friday, October 8, 2021 12:10 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Subject:</b> [PATCH 1/2] drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12</font>
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<div class="PlainText">It's used internally by firmware. Using it in the driver<br>
could conflict with firmware.<br>
<br>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 21 ++++++++++++---------<br>
1 file changed, 12 insertions(+), 9 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c<br>
index 91b3afa946f5..3b7775d74bb2 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c<br>
@@ -56,12 +56,15 @@<br>
* These are nbio v7_4_1 registers mask. Temporarily define these here since<br>
* nbio v7_4_1 header is incomplete.<br>
*/<br>
-#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L<br>
+#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L /* Don't use. Firmware uses this bit internally */<br>
#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L<br>
#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L<br>
#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L<br>
#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L<br>
#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L<br>
+#define GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK 0x00040000L<br>
+#define GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK 0x00080000L<br>
+#define GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK 0x00100000L<br>
<br>
#define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc<br>
#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2<br>
@@ -332,14 +335,14 @@ const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {<br>
.ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,<br>
.ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,<br>
.ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,<br>
- .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,<br>
- .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,<br>
- .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,<br>
- .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,<br>
- .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,<br>
- .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,<br>
- .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,<br>
- .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,<br>
+ .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,<br>
+ .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,<br>
+ .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,<br>
+ .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,<br>
+ .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,<br>
+ .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK,<br>
+ .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK,<br>
+ .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK,<br>
};<br>
<br>
static void nbio_v7_4_init_registers(struct amdgpu_device *adev)<br>
-- <br>
2.31.1<br>
<br>
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