<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="blue" vlink="purple" style="word-wrap:break-word"> <div class="WordSection1"> <p class="msipheadera4477989" style="margin:0in"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:blue">[AMD Official Use Only]</span><o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Thanks Tao.<o:p></o:p></p> <p class="MsoNormal">I will add a comment as you suggested before committing the change.<o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Regards,<o:p></o:p></p> <p class="MsoNormal">Mukul<o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <div style="border:none;border-left:solid blue 1.5pt;padding:0in 0in 0in 4.0pt"> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> <p class="MsoNormal"><b>From:</b> Zhou1, Tao <Tao.Zhou1@amd.com> <br> <b>Sent:</b> Monday, October 11, 2021 11:55 PM<br> <b>To:</b> Joshi, Mukul <Mukul.Joshi@amd.com>; amd-gfx@lists.freedesktop.org<br> <b>Cc:</b> Clements, John <John.Clements@amd.com><br> <b>Subject:</b> Re: [PATCH 2/2] drm/amdgpu: Fix RAS page retirement with mode2 reset on Aldebaran<o:p></o:p></p> </div> </div> <p class="MsoNormal"><o:p> </o:p></p> <p style="margin:5.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:blue">[AMD Official Use Only]<o:p></o:p></span></p> <p class="MsoNormal"><o:p> </o:p></p> <div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">The patch looks good for me, but it's better to add comment in amdgpu_register_bad_pages_mca_notifier to explain why we need to reserve GPU info instead of using mgpu_info list, with this addressed, the patch is:<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black;background:white">Reviewed-by: Tao Zhou <</span><span style="font-size:12.0pt;color:black"><a href="mailto:tao.zhou1@amd.com" target="_blank"><span style="background:white">tao.zhou1@amd.com</span></a><span style="background:white">></span><o:p></o:p></span></p> </div> <div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="divRplyFwdMsg"> <p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Joshi, Mukul <<a href="mailto:Mukul.Joshi@amd.com">Mukul.Joshi@amd.com</a>><br> <b>Sent:</b> Tuesday, October 12, 2021 10:33 AM<br> <b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br> <b>Cc:</b> Zhou1, Tao <<a href="mailto:Tao.Zhou1@amd.com">Tao.Zhou1@amd.com</a>>; Clements, John <<a href="mailto:John.Clements@amd.com">John.Clements@amd.com</a>>; Joshi, Mukul <<a href="mailto:Mukul.Joshi@amd.com">Mukul.Joshi@amd.com</a>><br> <b>Subject:</b> [PATCH 2/2] drm/amdgpu: Fix RAS page retirement with mode2 reset on Aldebaran</span> <o:p></o:p></p> <div> <p class="MsoNormal"> <o:p></o:p></p> </div> </div> <div> <div> <p class="MsoNormal" style="margin-bottom:12.0pt">During mode2 reset, the GPU is temporarily removed from the<br> mgpu_info list. As a result, page retirement fails because it<br> cannot find the GPU in the GPU list.<br> To fix this, create our own list of GPUs that support MCE notifier<br> based page retirement and use that list to check if the UMC error<br> occurred on a GPU that supports MCE notifier based page retirement.<br> <br> Signed-off-by: Mukul Joshi <<a href="mailto:mukul.joshi@amd.com">mukul.joshi@amd.com</a>><br> ---<br> drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 24 ++++++++++++------------<br> 1 file changed, 12 insertions(+), 12 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br> index e8875351967e..e8d88c77eb46 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c<br> @@ -112,7 +112,12 @@ static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,<br> static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,<br> uint64_t addr);<br> #ifdef CONFIG_X86_MCE_AMD<br> -static void amdgpu_register_bad_pages_mca_notifier(void);<br> +static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev);<br> +struct mce_notifier_adev_list {<br> + struct amdgpu_device *devs[MAX_GPU_INSTANCE];<br> + int num_gpu;<br> +};<br> +static struct mce_notifier_adev_list mce_adev_list;<br> #endif<br> <br> void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)<br> @@ -2108,7 +2113,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)<br> #ifdef CONFIG_X86_MCE_AMD<br> if ((adev->asic_type == CHIP_ALDEBARAN) &&<br> (adev->gmc.xgmi.connected_to_cpu))<br> - amdgpu_register_bad_pages_mca_notifier();<br> + amdgpu_register_bad_pages_mca_notifier(adev);<br> #endif<br> return 0;<br> <br> @@ -2605,24 +2610,18 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev)<br> #ifdef CONFIG_X86_MCE_AMD<br> static struct amdgpu_device *find_adev(uint32_t node_id)<br> {<br> - struct amdgpu_gpu_instance *gpu_instance;<br> int i;<br> struct amdgpu_device *adev = NULL;<br> <br> - mutex_lock(&mgpu_info.mutex);<br> -<br> - for (i = 0; i < mgpu_info.num_gpu; i++) {<br> - gpu_instance = &(mgpu_info.gpu_ins[i]);<br> - adev = gpu_instance->adev;<br> + for (i = 0; i < mce_adev_list.num_gpu; i++) {<br> + adev = mce_adev_list.devs[i];<br> <br> - if (adev->gmc.xgmi.connected_to_cpu &&<br> + if (adev && adev->gmc.xgmi.connected_to_cpu &&<br> adev->gmc.xgmi.physical_node_id == node_id)<br> break;<br> adev = NULL;<br> }<br> <br> - mutex_unlock(&mgpu_info.mutex);<br> -<br> return adev;<br> }<br> <br> @@ -2718,8 +2717,9 @@ static struct notifier_block amdgpu_bad_page_nb = {<br> .priority = MCE_PRIO_UC,<br> };<br> <br> -static void amdgpu_register_bad_pages_mca_notifier(void)<br> +static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev)<br> {<br> + mce_adev_list.devs[mce_adev_list.num_gpu++] = adev;<br> /*<br> * Register the x86 notifier only once<br> * with MCE subsystem.<br> -- <br> 2.33.0<o:p></o:p></p> </div> </div> </div> </div> </div> </div> </body> </html>