<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style>
</head>
<body dir="ltr">
<p style="font-family:Arial;font-size:10pt;color:#0000FF;margin:5pt;" align="Left">
[AMD Official Use Only]<br>
</p>
<br>
<div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
</div>
<div id="appendonsend"></div>
<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Lazar, Lijo <Lijo.Lazar@amd.com><br>
<b>Sent:</b> Monday, November 15, 2021 2:42 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; Quan, Evan <Evan.Quan@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/pm: Remove artificial freq level on Navi1x</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Print Navi1x fine grained clocks in a consistent manner with other SOCs.<br>
Don't show aritificial DPM level when the current clock equals min or max.<br>
<br>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com><br>
---<br>
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 13 ++++++++-----<br>
 1 file changed, 8 insertions(+), 5 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c<br>
index 71161f6b78fe..60a557068ea4 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c<br>
@@ -1265,7 +1265,7 @@ static int navi10_print_clk_levels(struct smu_context *smu,<br>
                         enum smu_clk_type clk_type, char *buf)<br>
 {<br>
         uint16_t *curve_settings;<br>
-       int i, size = 0, ret = 0;<br>
+       int i, levels, size = 0, ret = 0;<br>
         uint32_t cur_value = 0, value = 0, count = 0;<br>
         uint32_t freq_values[3] = {0};<br>
         uint32_t mark_index = 0;<br>
@@ -1319,14 +1319,17 @@ static int navi10_print_clk_levels(struct smu_context *smu,<br>
                         freq_values[1] = cur_value;<br>
                         mark_index = cur_value == freq_values[0] ? 0 :<br>
                                      cur_value == freq_values[2] ? 2 : 1;<br>
-                       if (mark_index != 1)<br>
-                               freq_values[1] = (freq_values[0] + freq_values[2]) / 2;<br>
 <br>
-                       for (i = 0; i < 3; i++) {<br>
+                       levels = 3;<br>
+                       if (mark_index != 1) {<br>
+                               levels = 2;<br>
+                               freq_values[1] = freq_values[2];<br>
+                       }<br>
+<br>
+                       for (i = 0; i < levels; i++) {<br>
                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],<br>
                                                 i == mark_index ? "*" : "");<br>
                         }<br>
-<br>
                 }<br>
                 break;<br>
         case SMU_PCIE:<br>
-- <br>
2.17.1<br>
<br>
</div>
</span></font></div>
</div>
</body>
</html>