<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style>
</head>
<body dir="ltr">
<p style="font-family:Arial;font-size:10pt;color:#0000FF;margin:5pt;" align="Left">
[AMD Official Use Only]<br>
</p>
<br>
<div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0); background-color: rgb(255, 255, 255);">
Reviewed-by: David Nieto <david.nieto@amd.com></div>
<div id="appendonsend"></div>
<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Skvortsov, Victor <Victor.Skvortsov@amd.com><br>
<b>Sent:</b> Wednesday, December 15, 2021 10:55 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Ming, Davis <Davis.Ming@amd.com>; Liu, Shaoyun <Shaoyun.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, JingWen
<JingWen.Chen2@amd.com>; Chen, Horace <Horace.Chen@amd.com>; Nieto, David M <David.Nieto@amd.com><br>
<b>Cc:</b> Skvortsov, Victor <Victor.Skvortsov@amd.com><br>
<b>Subject:</b> [PATCH 1/5] drm/amdgpu: Add *_SOC15_IP_NO_KIQ() macro definitions</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">Add helper macros to change register access<br>
from direct to indirect.<br>
<br>
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 5 +++++<br>
1 file changed, 5 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h<br>
index 8a9ca87d8663..473767e03676 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h<br>
@@ -51,6 +51,8 @@<br>
<br>
#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)<br>
<br>
+#define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP)<br>
+<br>
#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \<br>
__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \<br>
AMDGPU_REGS_NO_KIQ, ip##_HWIP)<br>
@@ -65,6 +67,9 @@<br>
#define WREG32_SOC15_IP(ip, reg, value) \<br>
__WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)<br>
<br>
+#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \<br>
+ __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)<br>
+<br>
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \<br>
__WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \<br>
value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)<br>
-- <br>
2.25.1<br>
<br>
</div>
</span></font></div>
</div>
</body>
</html>