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[AMD Official Use Only]<br>
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Reviewed-by: David Nieto <david.nieto@amd.com></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Skvortsov, Victor <Victor.Skvortsov@amd.com><br>
<b>Sent:</b> Wednesday, December 15, 2021 10:55 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Deng, Emily <Emily.Deng@amd.com>; Liu, Monk <Monk.Liu@amd.com>; Ming, Davis <Davis.Ming@amd.com>; Liu, Shaoyun <Shaoyun.Liu@amd.com>; Zhou, Peng Ju <PengJu.Zhou@amd.com>; Chen, JingWen
<JingWen.Chen2@amd.com>; Chen, Horace <Horace.Chen@amd.com>; Nieto, David M <David.Nieto@amd.com><br>
<b>Cc:</b> Skvortsov, Victor <Victor.Skvortsov@amd.com><br>
<b>Subject:</b> [PATCH 3/5] drm/amdgpu: Modify indirect register access for amdkfd_gfx_v9 sriov</font>
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<div class="PlainText">Modify GC register access from MMIO to RLCG if the indirect<br>
flag is set<br>
<br>
Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com><br>
---<br>
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 27 +++++++++----------<br>
1 file changed, 13 insertions(+), 14 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
index ddfe7aff919d..1abf662a0e91 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c<br>
@@ -166,7 +166,7 @@ int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id)<br>
<br>
lock_srbm(adev, mec, pipe, 0, 0);<br>
<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),<br>
+ WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,<br>
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |<br>
CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);<br>
<br>
@@ -279,7 +279,7 @@ int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd,<br>
lower_32_bits((uintptr_t)wptr));<br>
WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),<br>
upper_32_bits((uintptr_t)wptr));<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),<br>
+ WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,<br>
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));<br>
}<br>
<br>
@@ -488,13 +488,13 @@ bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev,<br>
uint32_t low, high;<br>
<br>
acquire_queue(adev, pipe_id, queue_id);<br>
- act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));<br>
+ act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);<br>
if (act) {<br>
low = lower_32_bits(queue_address >> 8);<br>
high = upper_32_bits(queue_address >> 8);<br>
<br>
- if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&<br>
- high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))<br>
+ if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&<br>
+ high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))<br>
retval = true;<br>
}<br>
release_queue(adev);<br>
@@ -556,7 +556,7 @@ int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd,<br>
<br>
end_jiffies = (utimeout * HZ / 1000) + jiffies;<br>
while (true) {<br>
- temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));<br>
+ temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);<br>
if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))<br>
break;<br>
if (time_after(jiffies, end_jiffies)) {<br>
@@ -645,7 +645,7 @@ int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev,<br>
mutex_lock(&adev->grbm_idx_mutex);<br>
<br>
WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);<br>
+ WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);<br>
<br>
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,<br>
INSTANCE_BROADCAST_WRITES, 1);<br>
@@ -722,7 +722,7 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx,<br>
pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe;<br>
queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe;<br>
soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0);<br>
- reg_val = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +<br>
+ reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, 0, mmSPI_CSQ_WF_ACTIVE_COUNT_0) +<br>
queue_slot);<br>
*wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK;<br>
if (*wave_cnt != 0)<br>
@@ -809,8 +809,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid,<br>
for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) {<br>
<br>
gfx_v9_0_select_se_sh(adev, se_idx, sh_idx, 0xffffffff);<br>
- queue_map = RREG32(SOC15_REG_OFFSET(GC, 0,<br>
- mmSPI_CSQ_WF_ACTIVE_STATUS));<br>
+ queue_map = RREG32_SOC15(GC, 0, mmSPI_CSQ_WF_ACTIVE_STATUS);<br>
<br>
/*<br>
* Assumption: queue map encodes following schema: four<br>
@@ -860,17 +859,17 @@ void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev,<br>
/*<br>
* Program TBA registers<br>
*/<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO),<br>
+ WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_LO,<br>
lower_32_bits(tba_addr >> 8));<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI),<br>
+ WREG32_SOC15(GC, 0, mmSQ_SHADER_TBA_HI,<br>
upper_32_bits(tba_addr >> 8));<br>
<br>
/*<br>
* Program TMA registers<br>
*/<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO),<br>
+ WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_LO,<br>
lower_32_bits(tma_addr >> 8));<br>
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI),<br>
+ WREG32_SOC15(GC, 0, mmSQ_SHADER_TMA_HI,<br>
upper_32_bits(tma_addr >> 8));<br>
<br>
unlock_srbm(adev);<br>
-- <br>
2.25.1<br>
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