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[Public]<br>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Bokun Zhang <Bokun.Zhang@amd.com><br>
<b>Sent:</b> Wednesday, December 15, 2021 7:52 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhang, Bokun <Bokun.Zhang@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: Filter security violation registers</font>
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<div class="PlainText">Recently, there is security policy update under SRIOV.<br>
We need to filter the registers that hit the violation<br>
and move the code to the host driver side so that<br>
the guest driver can execute correctly.<br>
<br>
Signed-off-by: Bokun Zhang <Bokun.Zhang@amd.com><br>
Change-Id: Ida893bb17de17a80e865c7662f04c5562f5d2727<br>
---<br>
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 83 ++++++++++++++------------<br>
 1 file changed, 46 insertions(+), 37 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c<br>
index 4f546f632223..d3d6d5b045b8 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c<br>
@@ -542,9 +542,6 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)<br>
         }<br>
 <br>
         for (i = 0; i < adev->sdma.num_instances; i++) {<br>
-               f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));<br>
-               f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,<br>
-                               AUTO_CTXSW_ENABLE, enable ? 1 : 0);<br>
                 if (enable && amdgpu_sdma_phase_quantum) {<br>
                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),<br>
                                phase_quantum);<br>
@@ -553,7 +550,13 @@ static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)<br>
                         WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),<br>
                                phase_quantum);<br>
                 }<br>
-               WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);<br>
+<br>
+               if (!amdgpu_sriov_vf(adev)) {<br>
+                       f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));<br>
+                       f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,<br>
+                                       AUTO_CTXSW_ENABLE, enable ? 1 : 0);<br>
+                       WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);<br>
+               }<br>
         }<br>
 <br>
 }<br>
@@ -576,10 +579,12 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)<br>
                 sdma_v5_2_rlc_stop(adev);<br>
         }<br>
 <br>
-       for (i = 0; i < adev->sdma.num_instances; i++) {<br>
-               f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));<br>
-               f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);<br>
-               WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);<br>
+       if (!amdgpu_sriov_vf(adev)) {<br>
+               for (i = 0; i < adev->sdma.num_instances; i++) {<br>
+                       f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));<br>
+                       f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);<br>
+                       WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);<br>
+               }<br>
         }<br>
 }<br>
 <br>
@@ -608,7 +613,8 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)<br>
                 ring = &adev->sdma.instance[i].ring;<br>
                 wb_offset = (ring->rptr_offs * 4);<br>
 <br>
-               WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);<br>
+               if (!amdgpu_sriov_vf(adev))<br>
+                       WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);<br>
 <br>
                 /* Set ring buffer size in dwords */<br>
                 rb_bufsz = order_base_2(ring->ring_size / 4);<br>
@@ -683,32 +689,34 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)<br>
                         sdma_v5_2_ring_set_wptr(ring);<br>
 <br>
                 /* set minor_ptr_update to 0 after wptr programed */<br>
-               WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);<br>
 <br>
-               /* set utc l1 enable flag always to 1 */<br>
-               temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));<br>
-               temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);<br>
-<br>
-               /* enable MCBP */<br>
-               temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);<br>
-               WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);<br>
-<br>
-               /* Set up RESP_MODE to non-copy addresses */<br>
-               temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));<br>
-               temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);<br>
-               temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);<br>
-               WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);<br>
-<br>
-               /* program default cache read and write policy */<br>
-               temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));<br>
-               /* clean read policy and write policy bits */<br>
-               temp &= 0xFF0FFF;<br>
-               temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |<br>
-                        (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |<br>
-                        SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);<br>
-               WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);<br>
+               WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);<br>
 <br>
+               /* SRIOV VF has no control of any of registers below */<br>
                 if (!amdgpu_sriov_vf(adev)) {<br>
+                       /* set utc l1 enable flag always to 1 */<br>
+                       temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));<br>
+                       temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);<br>
+<br>
+                       /* enable MCBP */<br>
+                       temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);<br>
+                       WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);<br>
+<br>
+                       /* Set up RESP_MODE to non-copy addresses */<br>
+                       temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));<br>
+                       temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);<br>
+                       temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);<br>
+                       WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);<br>
+<br>
+                       /* program default cache read and write policy */<br>
+                       temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));<br>
+                       /* clean read policy and write policy bits */<br>
+                       temp &= 0xFF0FFF;<br>
+                       temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |<br>
+                                (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |<br>
+                                SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);<br>
+                       WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);<br>
+<br>
                         /* unhalt engine */<br>
                         temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));<br>
                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);<br>
@@ -1436,13 +1444,14 @@ static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,<br>
                                         enum amdgpu_interrupt_state state)<br>
 {<br>
         u32 sdma_cntl;<br>
-<br>
         u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);<br>
 <br>
-       sdma_cntl = RREG32(reg_offset);<br>
-       sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,<br>
-                      state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);<br>
-       WREG32(reg_offset, sdma_cntl);<br>
+       if (!amdgpu_sriov_vf(adev)) {<br>
+               sdma_cntl = RREG32(reg_offset);<br>
+               sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,<br>
+                              state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);<br>
+               WREG32(reg_offset, sdma_cntl);<br>
+       }<br>
 <br>
         return 0;<br>
 }<br>
-- <br>
2.25.1<br>
<br>
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