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[Public]<br>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Quan, Evan <Evan.Quan@amd.com><br>
<b>Sent:</b> Friday, January 28, 2022 2:04 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Lazar, Lijo <Lijo.Lazar@amd.com>; Quan, Evan <Evan.Quan@amd.com><br>
<b>Subject:</b> [PATCH V3 2/7] drm/amd/pm: unify the interface for retrieving enabled ppfeatures</font>
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<div class="PlainText">Instead of having two which do the same thing.<br>
<br>
Signed-off-by: Evan Quan <evan.quan@amd.com><br>
Change-Id: I6302c9b5abdb999c4b7c83a0d1852181208b1c1f<br>
--<br>
v1->v2:<br>
  - use SMU IP version check rather than an asic type check(Alex)<br>
---<br>
 .../amd/pm/swsmu/smu11/cyan_skillfish_ppt.c   |  2 +-<br>
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  |  6 +-<br>
 .../drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c  |  6 +-<br>
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c        | 95 ++++++++-----------<br>
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h        |  4 -<br>
 5 files changed, 46 insertions(+), 67 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c<br>
index 2f57333e6071..cc080a0075ee 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/cyan_skillfish_ppt.c<br>
@@ -357,7 +357,7 @@ static bool cyan_skillfish_is_dpm_running(struct smu_context *smu)<br>
         if (adev->in_suspend)<br>
                 return false;<br>
 <br>
-       ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);<br>
+       ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);<br>
         if (ret)<br>
                 return false;<br>
 <br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c<br>
index 721027917f81..b4a3c9b8b54e 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c<br>
@@ -507,7 +507,7 @@ static bool vangogh_is_dpm_running(struct smu_context *smu)<br>
         if (adev->in_suspend)<br>
                 return false;<br>
 <br>
-       ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);<br>
+       ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);<br>
 <br>
         if (ret)<br>
                 return false;<br>
@@ -1965,7 +1965,7 @@ static int vangogh_system_features_control(struct smu_context *smu, bool en)<br>
         if (!en)<br>
                 return ret;<br>
 <br>
-       ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);<br>
+       ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);<br>
         if (ret)<br>
                 return ret;<br>
 <br>
@@ -2182,7 +2182,7 @@ static const struct pptable_funcs vangogh_ppt_funcs = {<br>
         .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,<br>
         .is_dpm_running = vangogh_is_dpm_running,<br>
         .read_sensor = vangogh_read_sensor,<br>
-       .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,<br>
+       .get_enabled_mask = smu_cmn_get_enabled_mask,<br>
         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,<br>
         .set_watermarks_table = vangogh_set_watermarks_table,<br>
         .set_driver_table_location = smu_v11_0_set_driver_table_location,<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c<br>
index bd24a2632214..f425827e2361 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c<br>
@@ -209,7 +209,7 @@ static int yellow_carp_system_features_control(struct smu_context *smu, bool en)<br>
         if (!en)<br>
                 return ret;<br>
 <br>
-       ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);<br>
+       ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);<br>
         if (ret)<br>
                 return ret;<br>
 <br>
@@ -258,7 +258,7 @@ static bool yellow_carp_is_dpm_running(struct smu_context *smu)<br>
         uint32_t feature_mask[2];<br>
         uint64_t feature_enabled;<br>
 <br>
-       ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);<br>
+       ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);<br>
 <br>
         if (ret)<br>
                 return false;<br>
@@ -1174,7 +1174,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = {<br>
         .is_dpm_running = yellow_carp_is_dpm_running,<br>
         .set_watermarks_table = yellow_carp_set_watermarks_table,<br>
         .get_gpu_metrics = yellow_carp_get_gpu_metrics,<br>
-       .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,<br>
+       .get_enabled_mask = smu_cmn_get_enabled_mask,<br>
         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,<br>
         .set_driver_table_location = smu_v13_0_set_driver_table_location,<br>
         .gfx_off_control = smu_v13_0_gfx_off_control,<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c<br>
index c3c679bf9d9f..c2e6c8b603da 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c<br>
@@ -545,67 +545,59 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,<br>
                              uint32_t *feature_mask,<br>
                              uint32_t num)<br>
 {<br>
-       uint32_t feature_mask_high = 0, feature_mask_low = 0;<br>
         struct smu_feature *feature = &smu->smu_feature;<br>
+       struct amdgpu_device *adev = smu->adev;<br>
+       uint32_t *feature_mask_high;<br>
+       uint32_t *feature_mask_low;<br>
         int ret = 0;<br>
 <br>
         if (!feature_mask || num < 2)<br>
                 return -EINVAL;<br>
 <br>
-       if (bitmap_empty(feature->enabled, feature->feature_num)) {<br>
-               ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesHigh, &feature_mask_high);<br>
-               if (ret)<br>
-                       return ret;<br>
-<br>
-               ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetEnabledSmuFeaturesLow, &feature_mask_low);<br>
-               if (ret)<br>
-                       return ret;<br>
-<br>
-               feature_mask[0] = feature_mask_low;<br>
-               feature_mask[1] = feature_mask_high;<br>
-       } else {<br>
-               bitmap_copy((unsigned long *)feature_mask, feature->enabled,<br>
+       if (!bitmap_empty(feature->enabled, feature->feature_num)) {<br>
+               bitmap_copy((unsigned long *)feature_mask,<br>
+                            feature->enabled,<br>
                              feature->feature_num);<br>
+               return 0;<br>
         }<br>
 <br>
-       return ret;<br>
-}<br>
-<br>
-int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,<br>
-                                       uint32_t *feature_mask,<br>
-                                       uint32_t num)<br>
-{<br>
-       uint32_t feature_mask_en_low = 0;<br>
-       uint32_t feature_mask_en_high = 0;<br>
-       struct smu_feature *feature = &smu->smu_feature;<br>
-       int ret = 0;<br>
-<br>
-       if (!feature_mask || num < 2)<br>
-               return -EINVAL;<br>
-<br>
-       if (bitmap_empty(feature->enabled, feature->feature_num)) {<br>
-               ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetEnabledSmuFeatures, 0,<br>
-                                                                                &feature_mask_en_low);<br>
+       feature_mask_low = &feature_mask[0];<br>
+       feature_mask_high = &feature_mask[1];<br>
 <br>
+       switch (adev->ip_versions[MP1_HWIP][0]) {<br>
+       case IP_VERSION(11, 0, 8):<br>
+       case IP_VERSION(11, 5, 0):<br>
+       case IP_VERSION(13, 0, 1):<br>
+       case IP_VERSION(13, 0, 3):<br>
+               ret = smu_cmn_send_smc_msg_with_param(smu,<br>
+                                                     SMU_MSG_GetEnabledSmuFeatures,<br>
+                                                     0,<br>
+                                                     feature_mask_low);<br>
                 if (ret)<br>
                         return ret;<br>
 <br>
-               ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetEnabledSmuFeatures, 1,<br>
-                                                                                &feature_mask_en_high);<br>
-<br>
+               ret = smu_cmn_send_smc_msg_with_param(smu,<br>
+                                                     SMU_MSG_GetEnabledSmuFeatures,<br>
+                                                     1,<br>
+                                                     feature_mask_high);<br>
+               break;<br>
+       case IP_VERSION(12, 0, 0):<br>
+       case IP_VERSION(12, 0, 1):<br>
+       /* other dGPU ASICs */<br>
+       default:<br>
+               ret = smu_cmn_send_smc_msg(smu,<br>
+                                          SMU_MSG_GetEnabledSmuFeaturesHigh,<br>
+                                          feature_mask_high);<br>
                 if (ret)<br>
                         return ret;<br>
 <br>
-               feature_mask[0] = feature_mask_en_low;<br>
-               feature_mask[1] = feature_mask_en_high;<br>
-<br>
-       } else {<br>
-               bitmap_copy((unsigned long *)feature_mask, feature->enabled,<br>
-                                feature->feature_num);<br>
+               ret = smu_cmn_send_smc_msg(smu,<br>
+                                          SMU_MSG_GetEnabledSmuFeaturesLow,<br>
+                                          feature_mask_low);<br>
+               break;<br>
         }<br>
 <br>
         return ret;<br>
-<br>
 }<br>
 <br>
 uint64_t smu_cmn_get_indep_throttler_status(<br>
@@ -710,20 +702,11 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,<br>
         size_t size = 0;<br>
         int ret = 0, i;<br>
 <br>
-       if (!smu->is_apu ||<br>
-           (smu->adev->asic_type == CHIP_RENOIR)) {<br>
-               ret = smu_cmn_get_enabled_mask(smu,<br>
-                                               feature_mask,<br>
-                                               2);<br>
-               if (ret)<br>
-                       return 0;<br>
-       } else {<br>
-               ret = smu_cmn_get_enabled_32_bits_mask(smu,<br>
-                                       feature_mask,<br>
-                                       2);<br>
-               if (ret)<br>
-                       return 0;<br>
-       }<br>
+       ret = smu_cmn_get_enabled_mask(smu,<br>
+                                      feature_mask,<br>
+                                      2);<br>
+       if (ret)<br>
+               return 0;<br>
 <br>
         size =  sysfs_emit_at(buf, size, "features high: 0x%08x low: 0x%08x\n",<br>
                         feature_mask[1], feature_mask[0]);<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h<br>
index f0b4fb2a0960..4e34c18c6063 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h<br>
@@ -61,10 +61,6 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,<br>
                              uint32_t *feature_mask,<br>
                              uint32_t num);<br>
 <br>
-int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,<br>
-                                       uint32_t *feature_mask,<br>
-                                       uint32_t num);<br>
-<br>
 uint64_t smu_cmn_get_indep_throttler_status(<br>
                                         const unsigned long dep_status,<br>
                                         const uint8_t *throttler_map);<br>
-- <br>
2.29.0<br>
<br>
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