<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style>
</head>
<body dir="ltr">
<p style="font-family:Arial;font-size:10pt;color:#008000;margin:15pt;" align="Left">
[Public]<br>
</p>
<br>
<div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
Please be sure to test this on other asics which use the HDP 4.0 code. I don't think this field exists for all of them.</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
<br>
</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
Alex</div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
<br>
</div>
<div id="appendonsend"></div>
<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Xiaogang.Chen <xiaogang.chen@amd.com><br>
<b>Sent:</b> Monday, February 21, 2022 6:05 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Chen, Xiaogang <Xiaogang.Chen@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix applications running across multiple GPU config hang.</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">From: Xiaogang Chen <xiaogang.chen@amd.com><br>
<br>
Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 1 +<br>
drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 2 ++<br>
2 files changed, 3 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c<br>
index d7811e0327cb..aa2c7c3f721f 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c<br>
@@ -145,6 +145,7 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev)<br>
}<br>
<br>
WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);<br>
+ WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);<br>
<br>
WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));<br>
WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h<br>
index 25e28691d62d..65c91b0102e4 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h<br>
@@ -104,6 +104,7 @@<br>
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5<br>
#define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6<br>
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb<br>
+#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe<br>
#define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15<br>
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17<br>
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18<br>
@@ -118,6 +119,7 @@<br>
#define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L<br>
#define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L<br>
#define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L<br>
+#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000c000L<br>
#define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L<br>
#define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L<br>
#define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L<br>
-- <br>
2.25.1<br>
<br>
</div>
</span></font></div>
</div>
</body>
</html>