<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="#0563C1" vlink="#954F72" style="word-wrap:break-word"> <div class="WordSection1"> <p class="msipheader23c54b6f" style="margin:0in"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:green">[Public]</span><o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">I think is safer only to set it for IP_VERSION(4, 4, 0): which is Aldebaran.<o:p></o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal"><o:p> </o:p></p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> <p class="MsoNormal"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> <b>On Behalf Of </b>Deucher, Alexander<br> <b>Sent:</b> Tuesday, February 22, 2022 8:55 AM<br> <b>To:</b> Chen, Xiaogang <Xiaogang.Chen@amd.com>; amd-gfx@lists.freedesktop.org<br> <b>Subject:</b> Re: [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix applications running across multiple GPU config hang.<o:p></o:p></p> </div> </div> <p class="MsoNormal"><o:p> </o:p></p> <p style="margin:15.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:green">[Public]<o:p></o:p></span></p> <p class="MsoNormal"><o:p> </o:p></p> <div> <p style="margin:15.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:green">[Public]<o:p></o:p></span></p> <p class="MsoNormal"><o:p> </o:p></p> <div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">Please be sure to test this on other asics which use the HDP 4.0 code. I don't think this field exists for all of them.<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black">Alex<o:p></o:p></span></p> </div> <div> <p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="divRplyFwdMsg"> <p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of Xiaogang.Chen <<a href="mailto:xiaogang.chen@amd.com">xiaogang.chen@amd.com</a>><br> <b>Sent:</b> Monday, February 21, 2022 6:05 PM<br> <b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br> <b>Cc:</b> Chen, Xiaogang <<a href="mailto:Xiaogang.Chen@amd.com">Xiaogang.Chen@amd.com</a>><br> <b>Subject:</b> [PATCH] drm/amdgpu: config HDP_MISC_CNTL.READ_BUFFER_WATERMARK to fix applications running across multiple GPU config hang.</span> <o:p></o:p></p> <div> <p class="MsoNormal"> <o:p></o:p></p> </div> </div> <div> <div> <p class="MsoNormal" style="margin-bottom:12.0pt">From: Xiaogang Chen <<a href="mailto:xiaogang.chen@amd.com">xiaogang.chen@amd.com</a>><br> <br> Signed-off-by: Xiaogang Chen <<a href="mailto:xiaogang.chen@amd.com">xiaogang.chen@amd.com</a>><br> ---<br> drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 1 +<br> drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 2 ++<br> 2 files changed, 3 insertions(+)<br> <br> diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c<br> index d7811e0327cb..aa2c7c3f721f 100644<br> --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c<br> +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c<br> @@ -145,6 +145,7 @@ static void hdp_v4_0_init_registers(struct amdgpu_device *adev)<br> }<br> <br> WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);<br> + WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, READ_BUFFER_WATERMARK, 2);<br> <br> WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));<br> WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));<br> diff --git a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h<br> index 25e28691d62d..65c91b0102e4 100644<br> --- a/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h<br> +++ b/drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h<br> @@ -104,6 +104,7 @@<br> #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5<br> #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6<br> #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb<br> +#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK__SHIFT 0xe<br> #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15<br> #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17<br> #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18<br> @@ -118,6 +119,7 @@<br> #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L<br> #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L<br> #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L<br> +#define HDP_MISC_CNTL__READ_BUFFER_WATERMARK_MASK 0x0000c000L<br> #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L<br> #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L<br> #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L<br> -- <br> 2.25.1<o:p></o:p></p> </div> </div> </div> </div> </div> </body> </html>