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[AMD Official Use Only]<br>
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Thank you for reviewing James!</div>
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Regards,</div>
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Rico</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Zhu, James <James.Zhu@amd.com><br>
<b>Sent:</b> Tuesday, March 15, 2022 20:01<br>
<b>To:</b> Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Chen, Guchun <Guchun.Chen@amd.com>; Zhu, James <James.Zhu@amd.com>; Wang, Yu (Charlie) <Yu.Wang4@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu/vcn: fix vcn ring test failure in igt reload test</font>
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<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">This patch is Reviewed-by: James Zhu <James.Zhu@amd.com><br>
<br>
On 2022-03-14 10:33 p.m., Tianci Yin wrote:<br>
> From: "Tianci.Yin" <tianci.yin@amd.com><br>
><br>
> [why]<br>
> On Renoir, vcn ring test failed on the second time insmod in the reload<br>
> test. After invetigation, it proves that vcn only can disable dpg under<br>
> dpg unpause mode (dpg unpause mode is default for dec only, dpg pause<br>
> mode is for dec/enc).<br>
><br>
> [how]<br>
> unpause dpg in dpg stopping procedure.<br>
><br>
> Change-Id: If6ec3af694e1d6b63ebce386a563f03ca6d291c1<br>
> Signed-off-by: Tianci.Yin <tianci.yin@amd.com><br>
> ---<br>
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 ++<br>
> 1 file changed, 2 insertions(+)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c<br>
> index 319ac8ea434b..6e0972cd1f2f 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c<br>
> @@ -1098,8 +1098,10 @@ static int vcn_v2_0_start(struct amdgpu_device *adev)<br>
> <br>
> static int vcn_v2_0_stop_dpg_mode(struct amdgpu_device *adev)<br>
> {<br>
> + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};<br>
> uint32_t tmp;<br>
> <br>
> + vcn_v2_0_pause_dpg_mode(adev, 0, &state);<br>
> /* Wait for power status to be 1 */<br>
> SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,<br>
> UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);<br>
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