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<p class="msipheadera4477989" style="margin:0in"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:blue">[AMD Official Use Only]</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Seems fine to me.<o:p></o:p></p>
<p class="MsoNormal">Series is reviewed-by: Evan Quan <evan.quan@amd.com><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thanks,<o:p></o:p></p>
<p class="MsoNormal">Evan<o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> Powell, Darren <Darren.Powell@amd.com> <br>
<b>Sent:</b> Friday, March 25, 2022 4:24 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Quan, Evan <Evan.Quan@amd.com><br>
<b>Subject:</b> Re: [PATCH v1 0/2] amdgpu/pm: Implement parallel sysfs_emit solution for vega10<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p style="margin:5.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:blue">[AMD Official Use Only]<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"> PING? <o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">** <a href="https://lore.kernel.org/amd-gfx/20220313052839.5777-1-darren.powell@amd.com/T/#u">
https://lore.kernel.org/amd-gfx/20220313052839.5777-1-darren.powell@amd.com/T/#u</a><o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"> [PATCH v1 0/2] amdgpu/pm: Implement parallel sysfs_emit solution for vega10
<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"> 2022-03-13 5:28 UTC (3+ messages)<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"> ` [PATCH 1/2] amdgpu/pm: Add new hwmgr API function "emit_clock_levels"<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"> ` [PATCH 2/2] amdgpu/pm: Implement emit_clk_levels for vega10<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"> Thanks<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black"> Darren<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Powell, Darren <<a href="mailto:Darren.Powell@amd.com">Darren.Powell@amd.com</a>><br>
<b>Sent:</b> Sunday, March 13, 2022 12:28 AM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Cc:</b> Powell, Darren <<a href="mailto:Darren.Powell@amd.com">Darren.Powell@amd.com</a>><br>
<b>Subject:</b> [PATCH v1 0/2] amdgpu/pm: Implement parallel sysfs_emit solution for vega10</span>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">== Description ==<br>
Scnprintf use within the kernel is not recommended, but simple sysfs_emit replacement has<br>
not been successful due to the page alignment requirement of the function. This patch<br>
set implements a new api "emit_clock_levels" to facilitate passing both the base and<br>
offset to the device rather than just the write pointer.<br>
<br>
The emit_clock_levels API for amdgpu_dpm has been duplicated to pp_dpm, based on the patch
<br>
commit 7f36948c92b2 ("amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset")<br>
and vega10_emit_clock_levels has been implemented with sysfs_emit based on vega10_print_clock_levels<br>
<br>
<br>
== Patch Summary ==<br>
linux: (<a href="mailto:git@gitlab.freedesktop.org:agd5f">git@gitlab.freedesktop.org:agd5f</a>) origin/amd-staging-drm-next @ 6b6b9c625004<br>
+ e94021f6c08c amdgpu/pm: Add new hwmgr API function "emit_clock_levels"<br>
+ d83131987718 amdgpu/pm: Implement emit_clk_levels for vega10<br>
<br>
== System Summary ==<br>
* DESKTOP(AMD FX-8350 + VEGA10(687f/c3), BIOS: F2)<br>
+ ISO(Ubuntu 20.04.4 LTS)<br>
+ Kernel(5.16.0-20220307-fdoagd5f-g6b6b9c625004)<br>
+ Overdrive Enabled(amdgpu.ppfeaturemask |= 0x4000)<br>
<br>
== Test ==<br>
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`<br>
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'`<br>
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}<br>
<br>
lspci -nn | grep "VGA\|Display" > $LOGFILE<br>
printf 'OD enabled = %X\n' "$(( `cat /sys/module/amdgpu/parameters/ppfeaturemask` & 0x4000 ))" >> $LOGFILE<br>
FILES="pp_od_clk_voltage<br>
pp_dpm_sclk<br>
pp_dpm_mclk<br>
pp_dpm_pcie<br>
pp_dpm_socclk<br>
pp_dpm_fclk<br>
pp_dpm_dcefclk<br>
pp_dpm_vclk<br>
pp_dpm_dclk "<br>
<br>
for f in $FILES<br>
do<br>
echo === $f === >> $LOGFILE<br>
cat $HWMON_DIR/device/$f >> $LOGFILE<br>
done<br>
cat $LOGFILE<br>
<br>
Darren Powell (2):<br>
amdgpu/pm: Add new hwmgr API function "emit_clock_levels"<br>
amdgpu/pm: Implement emit_clk_levels for vega10<br>
<br>
.../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 17 ++<br>
.../drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 147 ++++++++++++++++++<br>
drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h | 2 +<br>
3 files changed, 166 insertions(+)<br>
<br>
<br>
base-commit: 6b6b9c625004e07e000ca1918cadcb64439eb498<br>
-- <br>
2.35.1<o:p></o:p></p>
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