<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style>
</head>
<body dir="ltr">
<p style="font-family:Arial;font-size:10pt;color:#0000FF;margin:5pt;" align="Left">
[AMD Official Use Only]<br>
</p>
<br>
<div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
This<span style="color:silver"> </span>patch<span style="color:silver"> </span>is<span style="color:silver">
</span><span data-markjs="true" class="mark32y0ivcxs" data-ogac="" data-ogab="" data-ogsc="" data-ogsb="">Reviewed-by</span>:<span style="color:silver">
</span>James<span style="color:silver"> </span>Zhu<span style="color:silver"> </span>
<James.Zhu@amd.com> <br>
</div>
<div><br>
</div>
<div id="appendonsend"></div>
<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Tianci Yin <tianci.yin@amd.com><br>
<b>Sent:</b> Sunday, March 27, 2022 7:18 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Chen, Guchun <Guchun.Chen@amd.com>; Zhu, James <James.Zhu@amd.com>; Wang, Yu (Charlie) <Yu.Wang4@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/vcn: fix an error msg on vcn 3.0</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">From: tiancyin <tianci.yin@amd.com><br>
<br>
Some video card has more than one vcn instance, passing 0 to<br>
vcn_v3_0_pause_dpg_mode is incorrect.<br>
<br>
Error msg:<br>
Register(1) [mmUVD_POWER_STATUS] failed to reach value<br>
0x00000001 != 0x00000002<br>
<br>
Signed-off-by: tiancyin <tianci.yin@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 2 +-<br>
1 file changed, 1 insertion(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c<br>
index e1cca0a10653..cb5f0a12333f 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c<br>
@@ -1488,7 +1488,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)<br>
struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};<br>
uint32_t tmp;<br>
<br>
- vcn_v3_0_pause_dpg_mode(adev, 0, &state);<br>
+ vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);<br>
<br>
/* Wait for power status to be 1 */<br>
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,<br>
-- <br>
2.25.1<br>
<br>
</div>
</span></font></div>
</div>
</body>
</html>