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<div class="moz-cite-prefix">On 2022-04-04 12:19, Paul Menzel wrote:<br>
</div>
<blockquote type="cite" cite="mid:daeb333a-20b3-ca34-44e9-375f3b5ad2de@molgen.mpg.de">Dear
Philip,
<br>
<br>
<br>
Thank you for your patch.
<br>
<br>
Am 01.04.22 um 21:57 schrieb Philip Yang:
<br>
<blockquote type="cite">For VG20 + XGMI bridge, all mappings PTEs
cache in TC, this may have
<br>
stall invalid PTEs in TC because one cache line has 8 pages.
Need always
<br>
</blockquote>
<br>
Can you please rephrase. “may have stall …” is really hard to
understand.
<br>
</blockquote>
The patch already pushed and merged. <br>
<blockquote type="cite" cite="mid:daeb333a-20b3-ca34-44e9-375f3b5ad2de@molgen.mpg.de">
<br>
<blockquote type="cite">flush_tlb after updating mapping.
<br>
</blockquote>
<br>
Maybe:
<br>
<br>
So, always flush_tlb after updating the mapping.
<br>
<br>
<blockquote type="cite">Signed-off-by: Philip Yang
<a class="moz-txt-link-rfc2396E" href="mailto:Philip.Yang@amd.com"><Philip.Yang@amd.com></a>
<br>
---
<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++++
<br>
1 file changed, 6 insertions(+)
<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
<br>
index f0aec04111a3..687c9a140645 100644
<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
<br>
@@ -837,6 +837,12 @@ int amdgpu_vm_update_range(struct
amdgpu_device *adev, struct amdgpu_vm *vm,
<br>
goto error_unlock;
<br>
}
<br>
+ /* Vega20+XGMI where PTEs get inadvertently cached in L2
texture cache,
<br>
+ * heavy-weight flush TLB unconditionally.
<br>
+ */
<br>
+ flush_tlb |= (adev->gmc.xgmi.num_physical_nodes
&&
<br>
+ adev->ip_versions[GC_HWIP][0] == IP_VERSION(9,
4, 0));
<br>
+
<br>
memset(¶ms, 0, sizeof(params));
<br>
params.adev = adev;
<br>
params.vm = vm;
<br>
</blockquote>
<br>
Did you do any performance measurement, if that flushing affects
anything?
<br>
</blockquote>
<p>There was another patch to optimize TLB flush to improve map to
GPU performance, for this config, always flush TLB after updating
mapping is the original performance before the optimization.</p>
<p>Regards,</p>
<p>Philip<br>
</p>
<blockquote type="cite" cite="mid:daeb333a-20b3-ca34-44e9-375f3b5ad2de@molgen.mpg.de">
<br>
<br>
Kind regards,
<br>
<br>
Paul
<br>
</blockquote>
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