<html>
<head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<style type="text/css" style="display:none;"> P {margin-top:0;margin-bottom:0;} </style>
</head>
<body dir="ltr">
<p style="font-family:Arial;font-size:10pt;color:#0000FF;margin:5pt;" align="Left">
[AMD Official Use Only - General]<br>
</p>
<br>
<div>
<div style="font-family: Calibri, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
</div>
<div id="appendonsend"></div>
<hr style="display:inline-block;width:98%" tabindex="-1">
<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Joseph Greathouse <Joseph.Greathouse@amd.com><br>
<b>Sent:</b> Monday, June 6, 2022 7:04 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> StDenis, Tom <Tom.StDenis@amd.com>; Greathouse, Joseph <Joseph.Greathouse@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: Add MODE register to wave debug info in gfx11</font>
<div> </div>
</div>
<div class="BodyFragment"><font size="2"><span style="font-size:11pt;">
<div class="PlainText">All other chips, from gfx6-gfx10, now include the MODE register at the<br>
end of the wave debug state. This appears to have been missed in gfx11,<br>
so this patch adds in MODE to the debug state for gfx11.<br>
<br>
Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 1 +<br>
1 file changed, 1 insertion(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
index ca37289c644f..05359df6c354 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
@@ -1096,6 +1096,7 @@ static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd,<br>
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);<br>
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);<br>
dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);<br>
+ dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);<br>
}<br>
<br>
static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,<br>
-- <br>
2.20.1<br>
<br>
</div>
</span></font></div>
</div>
</body>
</html>