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[AMD Official Use Only - General]<br>
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will drop this single patch, and send out another independent patch for this.</div>
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Thanks,</div>
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Jack</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Yu, Lang <Lang.Yu@amd.com><br>
<b>Sent:</b> Wednesday, 29 June 2022 16:35<br>
<b>To:</b> Xiao, Jack <Jack.Xiao@amd.com><br>
<b>Cc:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Subject:</b> Re: [PATCH 6/7] drm/amdgpu/mes: add mes ring test</font>
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<div class="PlainText">On 06/29/ , Jack Xiao wrote:<br>
> Use read/write register to test mes ring.<br>
> <br>
> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com><br>
> ---<br>
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 36 +++++++++++++++++++++++++<br>
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 +<br>
> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 6 +++++<br>
> 3 files changed, 43 insertions(+)<br>
> <br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c<br>
> index b6c2a5058b64..c18ea0bc00eb 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c<br>
> @@ -926,6 +926,42 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,<br>
> return r;<br>
> }<br>
> <br>
> +int amdgpu_mes_ring_test_ring(struct amdgpu_device *adev)<br>
> +{<br>
> + uint32_t scratch;<br>
> + uint32_t tmp = 0;<br>
> + unsigned i;<br>
> + int r = 0;<br>
> +<br>
> + r = amdgpu_gfx_scratch_get(adev, &scratch);<br>
<br>
amdgpu_gfx_scratch_get/free() have been removed in latest amd-staging-drm-next.<br>
See e9b8129d8ca5 (drm/amdgpu: nuke dynamic gfx scratch reg allocation).<br>
<br>
Regards,<br>
Lang<br>
<br>
> + if (r) {<br>
> + DRM_ERROR("amdgpu: mes failed to get scratch reg (%d).\n", r);<br>
> + return r;<br>
> + }<br>
> +<br>
> + WREG32(scratch, 0xCAFEDEAD);<br>
> +<br>
> + tmp = amdgpu_mes_rreg(adev, scratch);<br>
> + if (tmp != 0xCAFEDEAD) {<br>
> + DRM_ERROR("mes failed to read register\n");<br>
> + goto error;<br>
> + }<br>
> +<br>
> + r = amdgpu_mes_wreg(adev, scratch, 0xDEADBEEF);<br>
> + if (r)<br>
> + goto error;<br>
> +<br>
> + tmp = RREG32(scratch);<br>
> + if (tmp != 0xDEADBEEF) {<br>
> + DRM_ERROR("mes failed to write register\n");<br>
> + r = -EIO;<br>
> + }<br>
> +<br>
> +error:<br>
> + amdgpu_gfx_scratch_free(adev, scratch);<br>
> + return r;<br>
> +}<br>
> +<br>
> static void<br>
> amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,<br>
> struct amdgpu_ring *ring,<br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h<br>
> index 93b2ba817916..81610e3f3059 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h<br>
> @@ -341,6 +341,7 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,<br>
> int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,<br>
> uint32_t reg0, uint32_t reg1,<br>
> uint32_t ref, uint32_t mask);<br>
> +int amdgpu_mes_ring_test_ring(struct amdgpu_device *adev);<br>
> <br>
> int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,<br>
> int queue_type, int idx,<br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c<br>
> index 2a6c7a680c62..c4d085429d26 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c<br>
> @@ -1194,6 +1194,12 @@ static int mes_v11_0_hw_init(void *handle)<br>
> goto failure;<br>
> }<br>
> <br>
> + r = amdgpu_mes_ring_test_ring(adev);<br>
> + if (r) {<br>
> + DRM_ERROR("MES ring test failed\n");<br>
> + goto failure;<br>
> + }<br>
> +<br>
> /*<br>
> * Disable KIQ ring usage from the driver once MES is enabled.<br>
> * MES uses KIQ ring exclusively so driver cannot access KIQ ring<br>
> -- <br>
> 2.35.1<br>
> <br>
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