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[AMD Official Use Only - General]<br>
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<div dir="ltr"><span style="caret-color:rgb(33, 33, 33);color:rgb(33, 33, 33);font-size:14.666666984558105px;display:inline !important">This series is:</span><br style="caret-color:rgb(33, 33, 33);color:rgb(33, 33, 33);font-size:14.666666984558105px">
<br style="caret-color:rgb(33, 33, 33);color:rgb(33, 33, 33);font-size:14.666666984558105px">
<span style="caret-color:rgb(33, 33, 33);color:rgb(33, 33, 33);font-size:14.666666984558105px;display:inline !important">Reviewed-by: Yifan Zhang</span></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>发件人:</b> Huang, Tim <Tim.Huang@amd.com><br>
<b>发送时间:</b> Thursday, August 18, 2022 10:17:32 AM<br>
<b>收件人:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>抄送:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Huang, Tim <Tim.Huang@amd.com><br>
<b>主题:</b> [PATCH 3/3] drm/amdgpu: enable NBIO IP v7.7.0 Clock Gating</font>
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<div class="PlainText">Enable AMD_CG_SUPPORT_BIF_MGCG and AMD_CG_SUPPORT_BIF_LS support.<br>
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Signed-off-by: Tim Huang <tim.huang@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/soc21.c | 7 +++----<br>
1 file changed, 3 insertions(+), 4 deletions(-)<br>
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diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c<br>
index 1ff7fc7bb340..982c12964879 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c<br>
@@ -603,6 +603,8 @@ static int soc21_common_early_init(void *handle)<br>
AMD_CG_SUPPORT_ATHUB_MGCG |<br>
AMD_CG_SUPPORT_ATHUB_LS |<br>
AMD_CG_SUPPORT_IH_CG |<br>
+ AMD_CG_SUPPORT_BIF_MGCG |<br>
+ AMD_CG_SUPPORT_BIF_LS |<br>
AMD_CG_SUPPORT_VCN_MGCG |<br>
AMD_CG_SUPPORT_JPEG_MGCG;<br>
adev->pg_flags =<br>
@@ -702,6 +704,7 @@ static int soc21_common_set_clockgating_state(void *handle,<br>
switch (adev->ip_versions[NBIO_HWIP][0]) {<br>
case IP_VERSION(4, 3, 0):<br>
case IP_VERSION(4, 3, 1):<br>
+ case IP_VERSION(7, 7, 0):<br>
adev->nbio.funcs->update_medium_grain_clock_gating(adev,<br>
state == AMD_CG_STATE_GATE);<br>
adev->nbio.funcs->update_medium_grain_light_sleep(adev,<br>
@@ -709,10 +712,6 @@ static int soc21_common_set_clockgating_state(void *handle,<br>
adev->hdp.funcs->update_clock_gating(adev,<br>
state == AMD_CG_STATE_GATE);<br>
break;<br>
- case IP_VERSION(7, 7, 0):<br>
- adev->hdp.funcs->update_clock_gating(adev,<br>
- state == AMD_CG_STATE_GATE);<br>
- break;<br>
default:<br>
break;<br>
}<br>
-- <br>
2.25.1<br>
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