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[AMD Official Use Only - General]<br>
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<div dir="ltr"><span style="color:rgb(33,33,33); font-size:14.67px; line-height:1.5">This series is:</span><br style="color:rgb(33,33,33)">
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<span style="color:rgb(33,33,33); font-size:14.67px; line-height:1.5">Reviewed-by: Yifan Zhang<span id="ms-outlook-ios-cursor"></span></span><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" color="#000000" style="font-size:11pt"><b>发件人:</b> Huang, Tim <Tim.Huang@amd.com><br>
<b>发送时间:</b> Monday, August 22, 2022 2:36:41 PM<br>
<b>收件人:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>抄送:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Du, Xiaojian <Xiaojian.Du@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Wenhui.Sheng@amd.com <Wenhui.Sheng@amd.com>; Huang, Tim <Tim.Huang@amd.com><br>
<b>主题:</b> [PATCH] drm/amdgpu: add sdma instance check for gfx11 CGCG</font>
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<div class="PlainText">For some ASICs, like GFX IP v11.0.1, only have one SDMA instance,<br>
so not need to configure SDMA1_RLC_CGCG_CTRL for this case.<br>
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Signed-off-by: Tim Huang <tim.huang@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 18 ++++++++++++------<br>
1 file changed, 12 insertions(+), 6 deletions(-)<br>
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diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
index f45db80810fa..e8db772e068c 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
@@ -5182,9 +5182,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade<br>
data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);<br>
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);<br>
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- data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);<br>
- data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);<br>
- WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);<br>
+ /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */<br>
+ if (adev->sdma.num_instances > 1) {<br>
+ data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);<br>
+ data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);<br>
+ WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);<br>
+ }<br>
} else {<br>
/* Program RLC_CGCG_CGLS_CTRL */<br>
def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);<br>
@@ -5213,9 +5216,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade<br>
data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;<br>
WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);<br>
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- data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);<br>
- data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;<br>
- WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);<br>
+ /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */<br>
+ if (adev->sdma.num_instances > 1) {<br>
+ data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);<br>
+ data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;<br>
+ WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);<br>
+ }<br>
}<br>
}<br>
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-- <br>
2.25.1<br>
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