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[Public]<br>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tom St Denis <tom.stdenis@amd.com><br>
<b>Sent:</b> Wednesday, September 7, 2022 10:22 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> StDenis, Tom <Tom.StDenis@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headers</font>
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<div class="PlainText">The TCC_DISABLE registers were not included in the 10.3 headers and<br>
instead just placed directly in the gfx_v10_0.c source. This patch<br>
adds them to the headers so tools like umr can scan them and support them.<br>
<br>
Signed-off-by: Tom St Denis <tom.stdenis@amd.com><br>
---<br>
.../gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h | 4 ++++<br>
.../drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h | 10 ++++++++++<br>
2 files changed, 14 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h<br>
index 594bffce93a9..1115dfc6ae1f 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h<br>
@@ -9800,6 +9800,10 @@<br>
<br>
// addressBlock: gc_pwrdec<br>
// base address: 0x3c000<br>
+#define mmCGTS_TCC_DISABLE 0x5006<br>
+#define mmCGTS_TCC_DISABLE_BASE_IDX 1<br>
+#define mmCGTS_USER_TCC_DISABLE 0x5007<br>
+#define mmCGTS_USER_TCC_DISABLE_BASE_IDX 1<br>
#define mmSQ_ALU_CLK_CTRL 0x508e<br>
#define mmSQ_ALU_CLK_CTRL_BASE_IDX 1<br>
#define mmSQ_TEX_CLK_CTRL 0x508f<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h<br>
index a827b0ff8905..83faa276523f 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_sh_mask.h<br>
@@ -34547,6 +34547,16 @@<br>
<br>
<br>
// addressBlock: gc_pwrdec<br>
+//CGTS_TCC_DISABLE<br>
+#define CGTS_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8<br>
+#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10<br>
+#define CGTS_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L<br>
+#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L<br>
+//CGTS_USER_TCC_DISABLE<br>
+#define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE__SHIFT 0x8<br>
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10<br>
+#define CGTS_USER_TCC_DISABLE__HI_TCC_DISABLE_MASK 0x0000FF00L<br>
+#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xFFFF0000L<br>
//SQ_ALU_CLK_CTRL<br>
#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA0__SHIFT 0x0<br>
#define SQ_ALU_CLK_CTRL__FORCE_WGP_ON_SA1__SHIFT 0x10<br>
-- <br>
2.34.1<br>
<br>
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