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[AMD Official Use Only - General]<br>
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<p class="MsoNormal"><span style="font-size:11.0pt">Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt">Regards,<br>
Hawking<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><b><span style="font-size:12.0pt;color:black">From:
</span></b><span style="font-size:12.0pt;color:black">amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Candice Li <Candice.Li@amd.com><br>
<b>Date: </b>Thursday, September 8, 2022 at 09:15<br>
<b>To: </b>amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc: </b>Li, Candice <Candice.Li@amd.com><br>
<b>Subject: </b>[PATCH] drm/amdgpu: Rely on MCUMC_STATUS for umc v8_10 correctable error counter only<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="font-size:11.0pt">Only check MCUMC_STATUS for CE counter for umc v8_10.<br>
<br>
Signed-off-by: Candice Li <candice.li@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/umc_v8_10.c | 12 +++---------<br>
1 file changed, 3 insertions(+), 9 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c<br>
index 36a2053f2e8b94..a8cbda81828daf 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/umc_v8_10.c<br>
@@ -101,22 +101,16 @@ static void umc_v8_10_query_correctable_error_count(struct amdgpu_device *adev,<br>
uint32_t umc_reg_offset,<br>
unsigned long *error_count)<br>
{<br>
- uint32_t ecc_err_cnt, ecc_err_cnt_addr;<br>
uint64_t mc_umc_status;<br>
uint32_t mc_umc_status_addr;<br>
<br>
/* UMC 8_10 registers */<br>
- ecc_err_cnt_addr =<br>
- SOC15_REG_OFFSET(UMC, 0, regUMCCH0_0_GeccErrCnt);<br>
mc_umc_status_addr =<br>
SOC15_REG_OFFSET(UMC, 0, regMCA_UMC_UMC0_MCUMC_STATUST0);<br>
<br>
- ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);<br>
- *error_count +=<br>
- (REG_GET_FIELD(ecc_err_cnt, UMCCH0_0_GeccErrCnt, GeccErrCnt) -<br>
- UMC_V8_10_CE_CNT_INIT);<br>
-<br>
- /* Check for SRAM correctable error, MCUMC_STATUS is a 64 bit register */<br>
+ /* Rely on MCUMC_STATUS for correctable error counter<br>
+ * MCUMC_STATUS is a 64 bit register<br>
+ */<br>
mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4);<br>
if (REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&<br>
REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)<br>
-- <br>
2.17.1<o:p></o:p></span></p>
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