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[AMD Official Use Only - General]<br>
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<p class="MsoNormal"><span style="font-size:11.0pt">Let’s create a new macro PSP_TMR_ALIGNMENT in case we need to support ASIC specific TMR alignment in future.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt">Regards,<br>
Hawking<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><b><span style="font-size:12.0pt;color:black">From:
</span></b><span style="font-size:12.0pt;color:black">Wang, Yang(Kevin) <KevinYang.Wang@amd.com><br>
<b>Date: </b>Friday, September 9, 2022 at 11:14<br>
<b>To: </b>amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc: </b>Zhang, Hawking <Hawking.Zhang@amd.com>, Wang, Yang(Kevin) <KevinYang.Wang@amd.com><br>
<b>Subject: </b>[PATCH] drm/amdgpu: change the alignment size of TMR BO to 1M<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="font-size:11.0pt">align TMR BO size TO tmr size is not necessary,<br>
modify the size to 1M to avoid re-create BO fail<br>
when serious VRAM fragmentation.<br>
<br>
Signed-off-by: Yang Wang <KevinYang.Wang@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +-<br>
1 file changed, 1 insertion(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
index cfcaf890a6a1..5585cda8d24b 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c<br>
@@ -766,7 +766,7 @@ static int psp_tmr_init(struct psp_context *psp)<br>
}<br>
<br>
pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;<br>
- ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),<br>
+ ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, SZ_1M,<br>
AMDGPU_GEM_DOMAIN_VRAM,<br>
&psp->tmr_bo, &psp->tmr_mc_addr, pptr);<br>
<br>
-- <br>
2.25.1<o:p></o:p></span></p>
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