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[Public]<br>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tom St Denis <tom.stdenis@amd.com><br>
<b>Sent:</b> Friday, September 23, 2022 8:56 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> StDenis, Tom <Tom.StDenis@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/amdgpu: Add missing XGMI hive registers for mmhub 9.4.1</font>
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<div class="PlainText">These are used by umr to sort the hive nodes since the kernel<br>
initializes the nodes in order of bus enumeration not XGMI hive<br>
enumeration.<br>
<br>
Signed-off-by: Tom St Denis <tom.stdenis@amd.com><br>
---<br>
.../drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h | 4 ++++<br>
.../drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h | 8 ++++++++<br>
2 files changed, 12 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h<br>
index d8632ccf3494..c488d4a50cf4 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_offset.h<br>
@@ -4409,6 +4409,10 @@<br>
#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1<br>
#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL 0x0af9<br>
#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1<br>
+#define mmMC_VM_XGMI_LFB_CNTL 0x0823<br>
+#define mmMC_VM_XGMI_LFB_CNTL_BASE_IDX 0<br>
+#define mmMC_VM_XGMI_LFB_SIZE 0x0824<br>
+#define mmMC_VM_XGMI_LFB_SIZE_BASE_IDX 0<br>
<br>
<br>
// addressBlock: mmhub_utcl2_vmsharedvcdec<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h<br>
index 111a71b434e2..2969fbf282b7 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_9_4_1_sh_mask.h<br>
@@ -26728,6 +26728,14 @@<br>
//VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL<br>
#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0<br>
#define VMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L<br>
+//MC_VM_XGMI_LFB_CNTL<br>
+#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0<br>
+#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x3<br>
+#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L<br>
+#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000038L<br>
+//MC_VM_XGMI_LFB_SIZE<br>
+#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0<br>
+#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL<br>
<br>
<br>
// addressBlock: mmhub_utcl2_vmsharedvcdec<br>
-- <br>
2.34.1<br>
<br>
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