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<p class="msipheaderc10f11a2" style="margin:0in"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:green">[Public]</span><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi Alex,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Sienna cichlid rlc firmware binary needs to be updated to match with the kernel change.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I shall add this comment to commit description.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<br>
Hawking<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in">
<p class="MsoNormal"><b>From:</b> Deucher, Alexander <Alexander.Deucher@amd.com> <br>
<b>Sent:</b> Saturday, September 24, 2022 05:36<br>
<b>To:</b> Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org; Gao, Likun <Likun.Gao@amd.com><br>
<b>Subject:</b> Re: [PATCH 09/10] drm/amdgpu/gfx10: switch to amdgpu_gfx_rlc_init_microcode<o:p></o:p></p>
</div>
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<p class="MsoNormal"><o:p> </o:p></p>
<p style="margin:15.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:green">[Public]<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<div>
<p class="MsoNormal"><span style="font-size:12.0pt;color:black">This set seems to break RLC firmware loading on sienna cichlid.<o:p></o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:12.0pt;color:black"><o:p> </o:p></span></p>
</div>
<div>
<p class="MsoNormal"><span style="font-size:12.0pt;color:black">Alex<o:p></o:p></span></p>
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<div class="MsoNormal" align="center" style="text-align:center">
<hr size="2" width="98%" align="center">
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<div id="divRplyFwdMsg">
<p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Zhang, Hawking <<a href="mailto:Hawking.Zhang@amd.com">Hawking.Zhang@amd.com</a>><br>
<b>Sent:</b> Thursday, September 15, 2022 1:01 PM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>>; Gao, Likun <<a href="mailto:Likun.Gao@amd.com">Likun.Gao@amd.com</a>>; Deucher, Alexander
<<a href="mailto:Alexander.Deucher@amd.com">Alexander.Deucher@amd.com</a>><br>
<b>Cc:</b> Zhang, Hawking <<a href="mailto:Hawking.Zhang@amd.com">Hawking.Zhang@amd.com</a>><br>
<b>Subject:</b> [PATCH 09/10] drm/amdgpu/gfx10: switch to amdgpu_gfx_rlc_init_microcode</span>
<o:p></o:p></p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<div>
<p class="MsoNormal" style="margin-bottom:12.0pt">switch to common helper to initialize rlc firmware<br>
for gfx10<br>
<br>
Signed-off-by: Hawking Zhang <<a href="mailto:Hawking.Zhang@amd.com">Hawking.Zhang@amd.com</a>><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 191 +------------------------<br>
1 file changed, 4 insertions(+), 187 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
index 26ec04fd313b..423b1b6d31b6 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c<br>
@@ -3943,56 +3943,6 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)<br>
DRM_WARN_ONCE("CP firmware version too old, please update!");<br>
}<br>
<br>
-<br>
-static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)<br>
-{<br>
- const struct rlc_firmware_header_v2_1 *rlc_hdr;<br>
-<br>
- rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;<br>
- adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);<br>
- adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);<br>
- adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);<br>
- adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);<br>
- adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);<br>
- adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);<br>
- adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);<br>
- adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);<br>
- adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);<br>
- adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);<br>
- adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);<br>
- adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);<br>
- adev->gfx.rlc.reg_list_format_direct_reg_list_length =<br>
- le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);<br>
-}<br>
-<br>
-static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)<br>
-{<br>
- const struct rlc_firmware_header_v2_2 *rlc_hdr;<br>
-<br>
- rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;<br>
- adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);<br>
- adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);<br>
- adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);<br>
- adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);<br>
-}<br>
-<br>
-static void gfx_v10_0_init_tap_delays_microcode(struct amdgpu_device *adev)<br>
-{<br>
- const struct rlc_firmware_header_v2_4 *rlc_hdr;<br>
-<br>
- rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;<br>
- adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);<br>
- adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);<br>
- adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);<br>
- adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);<br>
- adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);<br>
- adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);<br>
- adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);<br>
- adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);<br>
- adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);<br>
- adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);<br>
-}<br>
-<br>
static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)<br>
{<br>
bool ret = false;<br>
@@ -4032,8 +3982,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)<br>
const struct common_firmware_header *header = NULL;<br>
const struct gfx_firmware_header_v1_0 *cp_hdr;<br>
const struct rlc_firmware_header_v2_0 *rlc_hdr;<br>
- unsigned int *tmp = NULL;<br>
- unsigned int i = 0;<br>
uint16_t version_major;<br>
uint16_t version_minor;<br>
<br>
@@ -4123,59 +4071,14 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)<br>
if (err)<br>
goto out;<br>
err = amdgpu_ucode_validate(adev->gfx.rlc_fw);<br>
+ if (err)<br>
+ goto out;<br>
rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;<br>
version_major = le16_to_cpu(rlc_hdr->header.header_version_major);<br>
version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);<br>
-<br>
- adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);<br>
- adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);<br>
- adev->gfx.rlc.save_and_restore_offset =<br>
- le32_to_cpu(rlc_hdr->save_and_restore_offset);<br>
- adev->gfx.rlc.clear_state_descriptor_offset =<br>
- le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);<br>
- adev->gfx.rlc.avail_scratch_ram_locations =<br>
- le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);<br>
- adev->gfx.rlc.reg_restore_list_size =<br>
- le32_to_cpu(rlc_hdr->reg_restore_list_size);<br>
- adev->gfx.rlc.reg_list_format_start =<br>
- le32_to_cpu(rlc_hdr->reg_list_format_start);<br>
- adev->gfx.rlc.reg_list_format_separate_start =<br>
- le32_to_cpu(rlc_hdr->reg_list_format_separate_start);<br>
- adev->gfx.rlc.starting_offsets_start =<br>
- le32_to_cpu(rlc_hdr->starting_offsets_start);<br>
- adev->gfx.rlc.reg_list_format_size_bytes =<br>
- le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);<br>
- adev->gfx.rlc.reg_list_size_bytes =<br>
- le32_to_cpu(rlc_hdr->reg_list_size_bytes);<br>
- adev->gfx.rlc.register_list_format =<br>
- kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +<br>
- adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);<br>
- if (!adev->gfx.rlc.register_list_format) {<br>
- err = -ENOMEM;<br>
+ err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);<br>
+ if (err)<br>
goto out;<br>
- }<br>
-<br>
- tmp = (unsigned int *)((uintptr_t)rlc_hdr +<br>
- le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));<br>
- for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)<br>
- adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);<br>
-<br>
- adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;<br>
-<br>
- tmp = (unsigned int *)((uintptr_t)rlc_hdr +<br>
- le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));<br>
- for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)<br>
- adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);<br>
-<br>
- if (version_major == 2) {<br>
- if (version_minor >= 1)<br>
- gfx_v10_0_init_rlc_ext_microcode(adev);<br>
- if (version_minor >= 2)<br>
- gfx_v10_0_init_rlc_iram_dram_microcode(adev);<br>
- if (version_minor == 4) {<br>
- gfx_v10_0_init_tap_delays_microcode(adev);<br>
- }<br>
- }<br>
}<br>
<br>
snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);<br>
@@ -4228,92 +4131,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)<br>
adev->firmware.fw_size +=<br>
ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);<br>
<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];<br>
- info->ucode_id = AMDGPU_UCODE_ID_RLC_G;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- if (info->fw) {<br>
- header = (const struct common_firmware_header *)info->fw->data;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);<br>
- }<br>
- if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&<br>
- adev->gfx.rlc.save_restore_list_gpm_size_bytes &&<br>
- adev->gfx.rlc.save_restore_list_srm_size_bytes) {<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];<br>
- info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);<br>
-<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];<br>
- info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);<br>
-<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];<br>
- info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);<br>
-<br>
- if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&<br>
- adev->gfx.rlc.rlc_dram_ucode_size_bytes) {<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];<br>
- info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);<br>
-<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];<br>
- info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);<br>
- }<br>
-<br>
- }<br>
-<br>
- if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];<br>
- info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);<br>
- }<br>
-<br>
- if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];<br>
- info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);<br>
- }<br>
-<br>
- if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];<br>
- info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);<br>
- }<br>
-<br>
- if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];<br>
- info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);<br>
- }<br>
-<br>
- if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {<br>
- info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];<br>
- info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;<br>
- info->fw = adev->gfx.rlc_fw;<br>
- adev->firmware.fw_size +=<br>
- ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);<br>
- }<br>
-<br>
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];<br>
info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;<br>
info->fw = adev->gfx.mec_fw;<br>
-- <br>
2.17.1<o:p></o:p></p>
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