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[Public]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Zhang, Jesse(Jie) <Jesse.Zhang@amd.com><br>
<b>Sent:</b> Tuesday, October 11, 2022 1:23 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Kuehling, Felix <Felix.Kuehling@amd.com><br>
<b>Subject:</b> RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036</font>
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<p class="x_msipheaderdf3d92d6" style="margin:0cm"><span style="font-size:10.0pt; font-family:"Arial",sans-serif; color:blue">[AMD Official Use Only - General]</span></p>
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<p class="x_xmsonormal"> correct the cache information for gfx1036</p>
<p class="x_xmsonormal"> </p>
<p class="x_xmsonormal"> Signed-off-by: Yifan Zhang <a href="mailto:yifan1.zhang@amd.com">
yifan1.zhang@amd.com</a></p>
<p class="x_xmsonormal"> </p>
<p class="x_xmsonormal"> Signed-off-by: jie1zhan <a href="mailto:jesse.zhang@amd.com">
jesse.zhang@amd.com</a></p>
<p class="x_xmsonormal"> Change-Id: I60e754737057c144e69a6511ba6ddfca472ca7a1</p>
<p class="x_xmsonormal"> </p>
<p class="x_xmsonormal">diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c</p>
<p class="x_xmsonormal">index 477a30981c1b..d25ac9cbe5b2 100644</p>
<p class="x_xmsonormal">--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c</p>
<p class="x_xmsonormal">+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c</p>
<p class="x_xmsonormal">@@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {</p>
<p class="x_xmsonormal"> },</p>
<p class="x_xmsonormal">};</p>
<p class="x_xmsonormal"> </p>
<p class="x_xmsonormal">+static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {</p>
<p class="x_xmsonormal">+ {</p>
<p class="x_xmsonormal">+ /* TCP L1 Cache per CU */</p>
<p class="x_xmsonormal">+ .cache_size = 16,</p>
<p class="x_xmsonormal">+ .cache_level = 1,</p>
<p class="x_xmsonormal">+ .flags = (CRAT_CACHE_FLAGS_ENABLED |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_DATA_CACHE |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_SIMD_CACHE),</p>
<p class="x_xmsonormal">+ .num_cu_shared = 1,</p>
<p class="x_xmsonormal">+ },</p>
<p class="x_xmsonormal">+ {</p>
<p class="x_xmsonormal">+ /* Scalar L1 Instruction Cache per SQC */</p>
<p class="x_xmsonormal">+ .cache_size = 32,</p>
<p class="x_xmsonormal">+ .cache_level = 1,</p>
<p class="x_xmsonormal">+ .flags = (CRAT_CACHE_FLAGS_ENABLED |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_INST_CACHE |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_SIMD_CACHE),</p>
<p class="x_xmsonormal">+ .num_cu_shared = 2,</p>
<p class="x_xmsonormal">+ },</p>
<p class="x_xmsonormal">+ {</p>
<p class="x_xmsonormal">+ /* Scalar L1 Data Cache per SQC */</p>
<p class="x_xmsonormal">+ .cache_size = 16,</p>
<p class="x_xmsonormal">+ .cache_level = 1,</p>
<p class="x_xmsonormal">+ .flags = (CRAT_CACHE_FLAGS_ENABLED |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_DATA_CACHE |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_SIMD_CACHE),</p>
<p class="x_xmsonormal">+ .num_cu_shared = 2,</p>
<p class="x_xmsonormal">+ },</p>
<p class="x_xmsonormal">+ {</p>
<p class="x_xmsonormal">+ /* GL1 Data Cache per SA */</p>
<p class="x_xmsonormal">+ .cache_size = 128,</p>
<p class="x_xmsonormal">+ .cache_level = 1,</p>
<p class="x_xmsonormal">+ .flags = (CRAT_CACHE_FLAGS_ENABLED |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_DATA_CACHE |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_SIMD_CACHE),</p>
<p class="x_xmsonormal">+ .num_cu_shared = 2,</p>
<p class="x_xmsonormal">+ },</p>
<p class="x_xmsonormal">+ {</p>
<p class="x_xmsonormal">+ /* L2 Data Cache per GPU (Total Tex Cache) */</p>
<p class="x_xmsonormal">+ .cache_size = 256,</p>
<p class="x_xmsonormal">+ .cache_level = 2,</p>
<p class="x_xmsonormal">+ .flags = (CRAT_CACHE_FLAGS_ENABLED |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_DATA_CACHE |</p>
<p class="x_xmsonormal">+ CRAT_CACHE_FLAGS_SIMD_CACHE),</p>
<p class="x_xmsonormal">+ .num_cu_shared = 2,</p>
<p class="x_xmsonormal">+ },</p>
<p class="x_xmsonormal">+};</p>
<p class="x_xmsonormal">+</p>
<p class="x_xmsonormal">static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,</p>
<p class="x_xmsonormal"> struct crat_subtype_computeunit *cu)</p>
<p class="x_xmsonormal">{</p>
<p class="x_xmsonormal">@@ -1514,11 +1562,14 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,</p>
<p class="x_xmsonormal"> num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);</p>
<p class="x_xmsonormal"> break;</p>
<p class="x_xmsonormal"> case IP_VERSION(10, 3, 3):</p>
<p class="x_xmsonormal">- case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */</p>
<p class="x_xmsonormal"> case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */</p>
<p class="x_xmsonormal"> pcache_info = yellow_carp_cache_info;</p>
<p class="x_xmsonormal"> num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);</p>
<p class="x_xmsonormal"> break;</p>
<p class="x_xmsonormal">+ case IP_VERSION(10, 3, 6):</p>
<p class="x_xmsonormal">+ pcache_info = gc_10_3_6_cache_info;</p>
<p class="x_xmsonormal">+ num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);</p>
<p class="x_xmsonormal">+ break;</p>
<p class="x_xmsonormal"> case IP_VERSION(11, 0, 0):</p>
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