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[AMD Official Use Only - General]<br>
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Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com><br>
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--</div>
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Regards,</div>
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Aurabindo<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Sent:</b> Friday, January 27, 2023 1:05 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Pillai, Aurabindo <Aurabindo.Pillai@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/display: Properly handle additional cases where DCN is not supported</font>
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<div class="PlainText">There could be boards with DCN listed in IP discovery, but no<br>
display hardware actually wired up. In this case the vbios<br>
display table will not be populated. Detect this case and<br>
skip loading DM when we detect it.<br>
<br>
v2: Mark DCN as harvested as well so other display checks<br>
elsewhere in the driver are handled properly.<br>
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Cc: Aurabindo Pillai <aurabindo.pillai@amd.com><br>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com><br>
---<br>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++++++<br>
1 file changed, 11 insertions(+)<br>
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diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br>
index 42d99bf4bbc9..fe66b7aec248 100644<br>
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br>
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c<br>
@@ -4563,6 +4563,17 @@ static int dm_init_microcode(struct amdgpu_device *adev)<br>
static int dm_early_init(void *handle)<br>
{<br>
struct amdgpu_device *adev = (struct amdgpu_device *)handle;<br>
+ struct amdgpu_mode_info *mode_info = &adev->mode_info;<br>
+ struct atom_context *ctx = mode_info->atom_context;<br>
+ int index = GetIndexIntoMasterTable(DATA, Object_Header);<br>
+ u16 data_offset;<br>
+<br>
+ /* if there is no object header, skip DM */<br>
+ if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {<br>
+ adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;<br>
+ dev_info(adev->dev, "No object header, skipping DM\n");<br>
+ return -ENOENT;<br>
+ }<br>
<br>
switch (adev->asic_type) {<br>
#if defined(CONFIG_DRM_AMD_DC_SI)<br>
-- <br>
2.39.1<br>
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