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[AMD Official Use Only - General]<br>
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<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt">Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com><o:p></o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt"><o:p> </o:p></span></p>
<p class="MsoNormal"><span lang="EN-US" style="font-size:11.0pt">Regards,<br>
Hawking<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><b><span style="font-size:12.0pt;color:black">From:
</span></b><span style="font-size:12.0pt;color:black">Yifan Zha <Yifan.Zha@amd.com><br>
<b>Date: </b>Wednesday, February 1, 2023 at 13:15<br>
<b>To: </b>amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>, Deucher, Alexander <Alexander.Deucher@amd.com>, Zhang, Hawking <Hawking.Zhang@amd.com><br>
<b>Cc: </b>Chen, Horace <Horace.Chen@amd.com>, Chang, HaiJun <HaiJun.Chang@amd.com>, Zha, YiFan(Even) <Yifan.Zha@amd.com><br>
<b>Subject: </b>[PATCH v2] drm/amdgpu: Remove writing GRBM_GFX_CNTL in RLCG interface under SRIOV<o:p></o:p></span></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><span style="font-size:11.0pt">[Why]<br>
Accessing GRBM_GFX_CNTL in full access time has risk when VF is doing MMIO attacking.<br>
Therefore, VF writing GRBM_GFX_CNTL are blocked by L1 Policy.<br>
For RLCG interface, RLCG use SCRATCH_REG2 which is copied from GRBM_GFX_CNTL.<br>
<br>
[How]<br>
Remove writing GRBM_GFX_CNTL in amdgpu_virt_rlcg_reg_rw.<br>
<br>
v2:<br>
Remove directly writing GRBM_GFX_INDEX in amdgpu_virt_rlcg_reg_rw<br>
as RLCG interface no need to use it.<br>
<br>
Signed-off-by: Yifan Zha <Yifan.Zha@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 2 --<br>
1 file changed, 2 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c<br>
index f39391e03d46..ca5a1d026f5a 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c<br>
@@ -983,11 +983,9 @@ static u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v<br>
if (offset == reg_access_ctrl->grbm_cntl) {<br>
/* if the target reg offset is grbm_cntl, write to scratch_reg2 */<br>
writel(v, scratch_reg2);<br>
- writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));<br>
} else if (offset == reg_access_ctrl->grbm_idx) {<br>
/* if the target reg offset is grbm_idx, write to scratch_reg3 */<br>
writel(v, scratch_reg3);<br>
- writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));<br>
} else {<br>
/*<br>
* SCRATCH_REG0 = read/write value<br>
-- <br>
2.25.1<o:p></o:p></span></p>
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