<div dir="ltr">Reviewed-by: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Mar 23, 2023 at 5:41 PM Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Add UAPI to query the GFX shadow buffer requirements<br>
for preemption on GFX11. UMDs need to specify the shadow<br>
areas for preemption.<br>
<br>
v2: move into existing asic info query<br>
drop GDS as its use is determined by the UMD (Marek)<br>
<br>
Signed-off-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com" target="_blank">alexander.deucher@amd.com</a>><br>
---<br>
include/uapi/drm/amdgpu_drm.h | 8 ++++++++<br>
1 file changed, 8 insertions(+)<br>
<br>
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h<br>
index 3d9474af6566..3563c69521b0 100644<br>
--- a/include/uapi/drm/amdgpu_drm.h<br>
+++ b/include/uapi/drm/amdgpu_drm.h<br>
@@ -1136,6 +1136,14 @@ struct drm_amdgpu_info_device {<br>
__u64 mall_size; /* AKA infinity cache */<br>
/* high 32 bits of the rb pipes mask */<br>
__u32 enabled_rb_pipes_mask_hi;<br>
+ /* shadow area size for gfx11 */<br>
+ __u32 shadow_size;<br>
+ /* shadow area alignment for gfx11 */<br>
+ __u32 shadow_alignment;<br>
+ /* context save area size for gfx11 */<br>
+ __u32 csa_size;<br>
+ /* context save area alignment for gfx11 */<br>
+ __u32 csa_alignment;<br>
};<br>
<br>
struct drm_amdgpu_info_hw_ip {<br>
-- <br>
2.39.2<br>
<br>
</blockquote></div>