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[AMD Official Use Only - General]<br>
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Yep, we shall, thanks Alex.<br>
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Regards,</div>
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Jay<br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Alex Deucher <alexdeucher@gmail.com><br>
<b>Sent:</b> Tuesday, May 23, 2023 11:47 AM<br>
<b>To:</b> Pillai, Aurabindo <Aurabindo.Pillai@amd.com>; Mahfooz, Hamza <Hamza.Mahfooz@amd.com><br>
<b>Cc:</b> Michel Dänzer <michel@daenzer.net>; Deucher, Alexander <Alexander.Deucher@amd.com>; Chalmers, Wesley <Wesley.Chalmers@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Zhuo, Qingqing (Lillian) <Qingqing.Zhuo@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>;
amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Wentland, Harry <Harry.Wentland@amd.com><br>
<b>Subject:</b> Re: [PATCH 2/2] Revert "drm/amd/display: Do not set drr on pipe commit"</font>
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<div class="PlainText">Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
for the series.<br>
<br>
Jay, I assume you or Hamza will pick these up?<br>
<br>
Thanks,<br>
<br>
Alex<br>
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On Tue, May 23, 2023 at 11:31 AM Aurabindo Pillai<br>
<aurabindo.pillai@amd.com> wrote:<br>
><br>
> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com><br>
><br>
> On 5/22/23 09:08, Michel Dänzer wrote:<br>
> > From: Michel Dänzer <mdaenzer@redhat.com><br>
> ><br>
> > This reverts commit 474f01015ffdb74e01c2eb3584a2822c64e7b2be.<br>
> ><br>
> > Caused a regression:<br>
> ><br>
> > Samsung Odyssey Neo G9, running at 5120x1440@240/VRR, connected to Navi<br>
> > 21 via DisplayPort, blanks and the GPU hangs while starting the Steam<br>
> > game Assetto Corsa Competizione (via Proton 7.0).<br>
> ><br>
> > Example dmesg excerpt:<br>
> ><br>
> > amdgpu 0000:0c:00.0: [drm] ERROR [CRTC:82:crtc-0] flip_done timed out<br>
> > NMI watchdog: Watchdog detected hard LOCKUP on cpu 6<br>
> > [...]<br>
> > RIP: 0010:amdgpu_device_rreg.part.0+0x2f/0xf0 [amdgpu]<br>
> > Code: 41 54 44 8d 24 b5 00 00 00 00 55 89 f5 53 48 89 fb 4c 3b a7 60 0b 00 00 73 6a 83 e2 02 74 29 4c 03 a3 68 0b 00 00 45 8b 24 24 <48> 8b 43 08 0f b7 70 3e 66 90 44 89 e0 5b 5d 41 5c 31 d2 31 c9 31<br>
> > RSP: 0000:ffffb39a119dfb88 EFLAGS: 00000086<br>
> > RAX: ffffffffc0eb96a0 RBX: ffff9e7963dc0000 RCX: 0000000000007fff<br>
> > RDX: 0000000000000000 RSI: 0000000000004ff6 RDI: ffff9e7963dc0000<br>
> > RBP: 0000000000004ff6 R08: ffffb39a119dfc40 R09: 0000000000000010<br>
> > R10: ffffb39a119dfc40 R11: ffffb39a119dfc44 R12: 00000000000e05ae<br>
> > R13: 0000000000000000 R14: ffff9e7963dc0010 R15: 0000000000000000<br>
> > FS: 000000001012f6c0(0000) GS:ffff9e805eb80000(0000) knlGS:000000007fd40000<br>
> > CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033<br>
> > CR2: 00000000461ca000 CR3: 00000002a8a20000 CR4: 0000000000350ee0<br>
> > Call Trace:<br>
> > <TASK><br>
> > dm_read_reg_func+0x37/0xc0 [amdgpu]<br>
> > generic_reg_get2+0x22/0x60 [amdgpu]<br>
> > optc1_get_crtc_scanoutpos+0x6a/0xc0 [amdgpu]<br>
> > dc_stream_get_scanoutpos+0x74/0x90 [amdgpu]<br>
> > dm_crtc_get_scanoutpos+0x82/0xf0 [amdgpu]<br>
> > amdgpu_display_get_crtc_scanoutpos+0x91/0x190 [amdgpu]<br>
> > ? dm_read_reg_func+0x37/0xc0 [amdgpu]<br>
> > amdgpu_get_vblank_counter_kms+0xb4/0x1a0 [amdgpu]<br>
> > dm_pflip_high_irq+0x213/0x2f0 [amdgpu]<br>
> > amdgpu_dm_irq_handler+0x8a/0x200 [amdgpu]<br>
> > amdgpu_irq_dispatch+0xd4/0x220 [amdgpu]<br>
> > amdgpu_ih_process+0x7f/0x110 [amdgpu]<br>
> > amdgpu_irq_handler+0x1f/0x70 [amdgpu]<br>
> > __handle_irq_event_percpu+0x46/0x1b0<br>
> > handle_irq_event+0x34/0x80<br>
> > handle_edge_irq+0x9f/0x240<br>
> > __common_interrupt+0x66/0x110<br>
> > common_interrupt+0x5c/0xd0<br>
> > asm_common_interrupt+0x22/0x40<br>
> ><br>
> > Signed-off-by: Michel Dänzer <mdaenzer@redhat.com><br>
> > ---<br>
> > drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ------<br>
> > drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 7 -------<br>
> > 2 files changed, 13 deletions(-)<br>
> ><br>
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c<br>
> > index 6ce10fd4bb1a..5403e9399a46 100644<br>
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c<br>
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c<br>
> > @@ -2113,12 +2113,6 @@ void dcn20_optimize_bandwidth(<br>
> > if (hubbub->funcs->program_compbuf_size)<br>
> > hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);<br>
> ><br>
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {<br>
> > - dc_dmub_srv_p_state_delegate(dc,<br>
> > - true, context);<br>
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = true;<br>
> > - }<br>
> > -<br>
> > dc->clk_mgr->funcs->update_clocks(<br>
> > dc->clk_mgr,<br>
> > context,<br>
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c<br>
> > index 0411867654dd..0e071fbc9154 100644<br>
> > --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c<br>
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c<br>
> > @@ -985,18 +985,11 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,<br>
> > void dcn30_prepare_bandwidth(struct dc *dc,<br>
> > struct dc_state *context)<br>
> > {<br>
> > - if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {<br>
> > - dc->optimized_required = true;<br>
> > - context->bw_ctx.bw.dcn.clk.p_state_change_support = false;<br>
> > - }<br>
> > -<br>
> > if (dc->clk_mgr->dc_mode_softmax_enabled)<br>
> > if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&<br>
> > context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)<br>
> > dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);<br>
> ><br>
> > dcn20_prepare_bandwidth(dc, context);<br>
> > -<br>
> > - dc_dmub_srv_p_state_delegate(dc, false, context);<br>
> > }<br>
> ><br>
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