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[AMD Official Use Only - General]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com><br>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of jiadong.zhu@amd.com <jiadong.zhu@amd.com><br>
<b>Sent:</b> Wednesday, May 24, 2023 12:35 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhu, Jiadong <Jiadong.Zhu@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: Reset CP_VMID_PREEMPT after trailing fence signaled</font>
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<div class="PlainText">From: Jiadong Zhu <Jiadong.Zhu@amd.com><br>
<br>
When MEC executes unmap_queue for mid command buffer preemption, it will<br>
kick the write pointer of the gfx ring, set CP_VMID_PREEMPT to trigger the<br>
preemption and wait for CP_VMID_PREEMPT becomes zero after the preemption<br>
done. There is a race condition that PFP may excute the resetting command<br>
before MEC set CP_VMID_PREEMPT. As a result, hang happens as<br>
CP_VMID_PREEMPT is always 0xffff.<br>
<br>
To avoid this, we send resetting CP_VMID_PREEMPT command after the trailing<br>
fence is siganled and update gfx write pointer explicitly.<br>
<br>
Signed-off-by: Jiadong Zhu <Jiadong.Zhu@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++----<br>
1 file changed, 4 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
index 8bf95a6b0767..cbdd9918b3e7 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c<br>
@@ -5402,10 +5402,6 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring)<br>
amdgpu_ring_alloc(ring, 13);<br>
gfx_v9_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,<br>
ring->trail_seq, AMDGPU_FENCE_FLAG_EXEC | AMDGPU_FENCE_FLAG_INT);<br>
- /*reset the CP_VMID_PREEMPT after trailing fence*/<br>
- amdgpu_ring_emit_wreg(ring,<br>
- SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),<br>
- 0x0);<br>
<br>
/* assert IB preemption, emit the trailing fence */<br>
kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,<br>
@@ -5428,6 +5424,10 @@ static int gfx_v9_0_ring_preempt_ib(struct amdgpu_ring *ring)<br>
DRM_WARN("ring %d timeout to preempt ib\n", ring->idx);<br>
}<br>
<br>
+ /*reset the CP_VMID_PREEMPT after trailing fence*/<br>
+ amdgpu_ring_emit_wreg(ring,<br>
+ SOC15_REG_OFFSET(GC, 0, mmCP_VMID_PREEMPT),<br>
+ 0x0);<br>
amdgpu_ring_commit(ring);<br>
<br>
/* deassert preemption condition */<br>
-- <br>
2.25.1<br>
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