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[AMD Official Use Only - General]<br>
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This series is:</div>
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Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com><br>
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<p class="MsoAutoSig">Best Regards,</p>
<p class="MsoAutoSig">Yifan</p>
<p class="MsoAutoSig"><o:p> </o:p></p>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Huang, Tim <Tim.Huang@amd.com><br>
<b>Sent:</b> Friday, June 9, 2023 6:44 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Zhang, Jesse(Jie) <Jesse.Zhang@amd.com>; Huang, Tim <Tim.Huang@amd.com><br>
<b>Subject:</b> [PATCH 3/3] drm/amd/pm: enable more Pstates profile levels for SMU v13.0.5</font>
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<div class="PlainText">This patch enables following UMD stable Pstates profile<br>
levels for power_dpm_force_performance_level interface.<br>
<br>
- profile_peak<br>
- profile_min_sclk<br>
- profile_standard<br>
<br>
Signed-off-by: Tim Huang <Tim.Huang@amd.com><br>
---<br>
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c | 40 ++++++++++++++++++-<br>
.../drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h | 2 +-<br>
2 files changed, 39 insertions(+), 3 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c<br>
index 53c508acf895..42f110602eb1 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.c<br>
@@ -978,6 +978,38 @@ static int smu_v13_0_5_force_clk_levels(struct smu_context *smu,<br>
return ret;<br>
}<br>
<br>
+static int smu_v13_0_5_get_dpm_profile_freq(struct smu_context *smu,<br>
+ enum amd_dpm_forced_level level,<br>
+ enum smu_clk_type clk_type,<br>
+ uint32_t *min_clk,<br>
+ uint32_t *max_clk)<br>
+{<br>
+ int ret = 0;<br>
+ uint32_t clk_limit = 0;<br>
+<br>
+ switch (clk_type) {<br>
+ case SMU_GFXCLK:<br>
+ case SMU_SCLK:<br>
+ clk_limit = SMU_13_0_5_UMD_PSTATE_GFXCLK;<br>
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)<br>
+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &clk_limit);<br>
+ else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)<br>
+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_SCLK, &clk_limit, NULL);<br>
+ break;<br>
+ case SMU_VCLK:<br>
+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &clk_limit);<br>
+ break;<br>
+ case SMU_DCLK:<br>
+ smu_v13_0_5_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &clk_limit);<br>
+ break;<br>
+ default:<br>
+ ret = -EINVAL;<br>
+ break;<br>
+ }<br>
+ *min_clk = *max_clk = clk_limit;<br>
+ return ret;<br>
+}<br>
+<br>
static int smu_v13_0_5_set_performance_level(struct smu_context *smu,<br>
enum amd_dpm_forced_level level)<br>
{<br>
@@ -1011,10 +1043,14 @@ static int smu_v13_0_5_set_performance_level(struct smu_context *smu,<br>
break;<br>
case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:<br>
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:<br>
- case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:<br>
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:<br>
- /* Temporarily do nothing since the optimal clocks haven't been provided yet */<br>
+ smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_SCLK, &sclk_min, &sclk_max);<br>
+ smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_VCLK, &vclk_min, &vclk_max);<br>
+ smu_v13_0_5_get_dpm_profile_freq(smu, level, SMU_DCLK, &dclk_min, &dclk_max);<br>
break;<br>
+ case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:<br>
+ dev_err(adev->dev, "The performance level profile_min_mclk is not supported.");<br>
+ return -EOPNOTSUPP;<br>
case AMD_DPM_FORCED_LEVEL_MANUAL:<br>
case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:<br>
return 0;<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h<br>
index 40bc0f8e6d61..263cd651855e 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_5_ppt.h<br>
@@ -24,6 +24,6 @@<br>
#define __SMU_V13_0_5_PPT_H__<br>
<br>
extern void smu_v13_0_5_set_ppt_funcs(struct smu_context *smu);<br>
-#define SMU_13_0_5_UMD_PSTATE_GFXCLK 1100<br>
+#define SMU_13_0_5_UMD_PSTATE_GFXCLK 700<br>
<br>
#endif<br>
-- <br>
2.34.1<br>
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