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<p style="font-family:Arial;font-size:10pt;color:#0000FF;margin:5pt;font-style:normal;font-weight:normal;text-decoration:none;" align="Left">
[AMD Official Use Only - General]<br>
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<p class="MsoNormal">Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org>
<b>On Behalf Of </b>Deucher, Alexander<br>
<b>Sent:</b> Thursday, July 27, 2023 9:30 AM<br>
<b>To:</b> Feng, Kenneth <Kenneth.Feng@amd.com>; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> Quan, Evan <Evan.Quan@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amd/pm: correct the pcie width for smu 13.0.0<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p style="margin:5.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:blue">[AMD Official Use Only - General]<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p style="margin:5.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:blue">[AMD Official Use Only - General]<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">Acked-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> amd-gfx <<a href="mailto:amd-gfx-bounces@lists.freedesktop.org">amd-gfx-bounces@lists.freedesktop.org</a>> on behalf of Kenneth Feng <<a href="mailto:kenneth.feng@amd.com">kenneth.feng@amd.com</a>><br>
<b>Sent:</b> Thursday, July 27, 2023 7:41 AM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Cc:</b> Quan, Evan <<a href="mailto:Evan.Quan@amd.com">Evan.Quan@amd.com</a>>; Feng, Kenneth <<a href="mailto:Kenneth.Feng@amd.com">Kenneth.Feng@amd.com</a>><br>
<b>Subject:</b> [PATCH] drm/amd/pm: correct the pcie width for smu 13.0.0</span> <o:p>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">correct the pcie width value in pp_dpm_pcie for smu 13.0.0<br>
<br>
Signed-off-by: Kenneth Feng <<a href="mailto:kenneth.feng@amd.com">kenneth.feng@amd.com</a>><br>
---<br>
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 +--<br>
1 file changed, 1 insertion(+), 2 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c<br>
index 232274423f9e..4bdbd3910e1f 100644<br>
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c<br>
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c<br>
@@ -1140,7 +1140,6 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,<br>
(OverDriveTableExternal_t *)smu->smu_table.overdrive_table;<br>
struct smu_13_0_dpm_table *single_dpm_table;<br>
struct smu_13_0_pcie_table *pcie_table;<br>
- const int link_width[] = {0, 1, 2, 4, 8, 12, 16};<br>
uint32_t gen_speed, lane_width;<br>
int i, curr_freq, size = 0;<br>
int32_t min_value, max_value;<br>
@@ -1256,7 +1255,7 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,<br>
(pcie_table->pcie_lane[i] == 6) ? "x16" : "",<br>
pcie_table->clk_freq[i],<br>
(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&<br>
- (lane_width == DECODE_LANE_WIDTH(link_width[pcie_table->pcie_lane[i]])) ?<br>
+ (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?<br>
"*" : "");<br>
break;<br>
<br>
-- <br>
2.34.1<o:p></o:p></p>
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