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[Public]<br>
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<div class="elementToProof"><span style="letter-spacing: normal; font-family: "Segoe UI", "Segoe UI Web (West European)", "Segoe UI", -apple-system, BlinkMacSystemFont, Roboto, "Helvetica Neue", sans-serif; font-size: 14.6667px; font-weight: 400; color: rgb(36, 36, 36); background-color: rgb(255, 255, 255);"> enum
amd_ip_block_type</span> doc is missing for LSDMA.</div>
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<div class="elementToProof">@@ -85,6 +85,7 @@ enum amd_apu_flags {</div>
<div> * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine</div>
<div> * @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine</div>
<div> * @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Schduler for Multimedia</div>
<div>+* @AMD_IP_BLOCK_TYPE_LSDMA:</div>
<div> * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types</div>
<div> */</div>
<div class="elementToProof"> enum amd_ip_block_type {</div>
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</div>
<div class="elementToProof"><span style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">With that fixed the series is Reviewed-by: Lang Yu <lang.yu@amd.com>.</span></div>
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<div class="elementToProof" style="font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Zhang, Yifan <Yifan1.Zhang@amd.com><br>
<b>Sent:</b> Friday, November 17, 2023 10:09 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Huang, Tim <Tim.Huang@amd.com>; Yu, Lang <Lang.Yu@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com><br>
<b>Subject:</b> [PATCH v2 1/6] drm/amdgpu: add lsdma hw ip definition</font>
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<div class="PlainText">This patch is to add lsdma hw ip definition.<br>
<br>
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com><br>
Reviewed-by: Tim Huang <Tim.Huang@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 1 +<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 15 +++++++++++++++<br>
drivers/gpu/drm/amd/include/amd_shared.h | 1 +<br>
include/uapi/drm/amdgpu_drm.h | 3 ++-<br>
5 files changed, 20 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<br>
index b49ad7690a8c..bba9e8da2384 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c<br>
@@ -3418,6 +3418,7 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev)<br>
AMD_IP_BLOCK_TYPE_DCE,<br>
AMD_IP_BLOCK_TYPE_GFX,<br>
AMD_IP_BLOCK_TYPE_SDMA,<br>
+ AMD_IP_BLOCK_TYPE_LSDMA,<br>
AMD_IP_BLOCK_TYPE_MES,<br>
AMD_IP_BLOCK_TYPE_UVD,<br>
AMD_IP_BLOCK_TYPE_VCE,<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c<br>
index b3630ceaff4c..20519ca90fb5 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c<br>
@@ -52,6 +52,7 @@ static const char *amdgpu_ip_name[AMDGPU_HW_IP_NUM] = {<br>
[AMDGPU_HW_IP_VCN_ENC] = "enc",<br>
[AMDGPU_HW_IP_VCN_JPEG] = "jpeg",<br>
[AMDGPU_HW_IP_VPE] = "vpe",<br>
+ [AMDGPU_HW_IP_LSDMA] = "lsdma",<br>
};<br>
<br>
void amdgpu_show_fdinfo(struct seq_file *m, struct file *f)<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
index b5ebafd4a3ad..91ec481377fa 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
@@ -215,6 +215,9 @@ static enum amd_ip_block_type<br>
case AMDGPU_HW_IP_DMA:<br>
type = AMD_IP_BLOCK_TYPE_SDMA;<br>
break;<br>
+ case AMDGPU_HW_IP_LSDMA:<br>
+ type = AMD_IP_BLOCK_TYPE_LSDMA;<br>
+ break;<br>
case AMDGPU_HW_IP_UVD:<br>
case AMDGPU_HW_IP_UVD_ENC:<br>
type = AMD_IP_BLOCK_TYPE_UVD;<br>
@@ -438,6 +441,13 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,<br>
ib_start_alignment = 256;<br>
ib_size_alignment = 4;<br>
break;<br>
+ case AMDGPU_HW_IP_LSDMA:<br>
+ type = AMD_IP_BLOCK_TYPE_LSDMA;<br>
+ if (adev->lsdma.ring.sched.ready)<br>
+ ++num_rings;<br>
+ ib_start_alignment = 256;<br>
+ ib_size_alignment = 4;<br>
+ break;<br>
case AMDGPU_HW_IP_UVD:<br>
type = AMD_IP_BLOCK_TYPE_UVD;<br>
for (i = 0; i < adev->uvd.num_uvd_inst; i++) {<br>
@@ -546,6 +556,10 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,<br>
result->ip_discovery_version =<br>
IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, SDMA0_HWIP, 0));<br>
break;<br>
+ case AMD_IP_BLOCK_TYPE_LSDMA:<br>
+ result->ip_discovery_version =<br>
+ IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, LSDMA_HWIP, 0));<br>
+ break;<br>
case AMD_IP_BLOCK_TYPE_UVD:<br>
case AMD_IP_BLOCK_TYPE_VCN:<br>
case AMD_IP_BLOCK_TYPE_JPEG:<br>
@@ -679,6 +693,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)<br>
switch (type) {<br>
case AMD_IP_BLOCK_TYPE_GFX:<br>
case AMD_IP_BLOCK_TYPE_VCE:<br>
+ case AMD_IP_BLOCK_TYPE_LSDMA:<br>
count = 1;<br>
break;<br>
case AMD_IP_BLOCK_TYPE_SDMA:<br>
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h<br>
index 579977f6ad52..8c03afd4d472 100644<br>
--- a/drivers/gpu/drm/amd/include/amd_shared.h<br>
+++ b/drivers/gpu/drm/amd/include/amd_shared.h<br>
@@ -95,6 +95,7 @@ enum amd_ip_block_type {<br>
AMD_IP_BLOCK_TYPE_PSP,<br>
AMD_IP_BLOCK_TYPE_DCE,<br>
AMD_IP_BLOCK_TYPE_GFX,<br>
+ AMD_IP_BLOCK_TYPE_LSDMA,<br>
AMD_IP_BLOCK_TYPE_SDMA,<br>
AMD_IP_BLOCK_TYPE_UVD,<br>
AMD_IP_BLOCK_TYPE_VCE,<br>
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h<br>
index ad21c613fec8..8edae0f56bdd 100644<br>
--- a/include/uapi/drm/amdgpu_drm.h<br>
+++ b/include/uapi/drm/amdgpu_drm.h<br>
@@ -595,7 +595,8 @@ struct drm_amdgpu_gem_va {<br>
#define AMDGPU_HW_IP_VCN_ENC 7<br>
#define AMDGPU_HW_IP_VCN_JPEG 8<br>
#define AMDGPU_HW_IP_VPE 9<br>
-#define AMDGPU_HW_IP_NUM 10<br>
+#define AMDGPU_HW_IP_LSDMA 10<br>
+#define AMDGPU_HW_IP_NUM 11<br>
<br>
#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1<br>
<br>
-- <br>
2.37.3<br>
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