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[AMD Official Use Only - General]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Zhang, Yifan <Yifan1.Zhang@amd.com><br>
<b>Sent:</b> Monday, January 29, 2024 4:06 AM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Deucher, Alexander <Alexander.Deucher@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Huang, Tim <Tim.Huang@amd.com>; Yu, Lang <Lang.Yu@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: remove golden setting for gfx 11.5.0</font>
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<div class="PlainText">No need to set golden settings in driver from gfx 11.5.0 onwards<br>
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Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 32 ++------------------------<br>
1 file changed, 2 insertions(+), 30 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
index c1e000010760..4e99af904e04 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c<br>
@@ -90,10 +90,6 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");<br>
MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");<br>
MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");<br>
<br>
-static const struct soc15_reg_golden golden_settings_gc_11_0[] = {<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)<br>
-};<br>
-<br>
static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =<br>
{<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),<br>
@@ -104,24 +100,8 @@ static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)<br>
-};<br>
-<br>
-static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = {<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff, 0x00000800),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb, 0x00f40188),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x80009007),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff, 0x00880007),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff, 0x00010000),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000, 0x00000000),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff, 0x0000200a),<br>
- SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff, 0x0000048f)<br>
+ SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a),<br>
+ SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)<br>
};<br>
<br>
#define DEFAULT_SH_MEM_CONFIG \<br>
@@ -304,17 +284,9 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)<br>
golden_settings_gc_11_0_1,<br>
(const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));<br>
break;<br>
- case IP_VERSION(11, 5, 0):<br>
- soc15_program_register_sequence(adev,<br>
- golden_settings_gc_11_5_0,<br>
- (const u32)ARRAY_SIZE(golden_settings_gc_11_5_0));<br>
- break;<br>
default:<br>
break;<br>
}<br>
- soc15_program_register_sequence(adev,<br>
- golden_settings_gc_11_0,<br>
- (const u32)ARRAY_SIZE(golden_settings_gc_11_0));<br>
<br>
}<br>
<br>
-- <br>
2.37.3<br>
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