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<p style="font-family:Arial;font-size:10pt;color:#0000FF;margin:5pt;font-style:normal;font-weight:normal;text-decoration:none;" align="Left">
[AMD Official Use Only - General]<br>
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<p class="MsoNormal"><span style="color:#1F4E79">Reviewed By Zhigang Luo <Zhigang.Luo@amd.com><o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F4E79"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b>From:</b> Lu, Victor Cheng Chi (Victor) <VictorChengChi.Lu@amd.com>
<br>
<b>Sent:</b> Friday, February 16, 2024 1:50 PM<br>
<b>To:</b> Luo, Zhigang <Zhigang.Luo@amd.com><br>
<b>Subject:</b> Fw: [PATCH 3/4] drm/amdgpu: Use correct SRIOV macro for gmc_v9_0_vm_fault_interrupt_state<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p style="margin:5.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:blue">[AMD Official Use Only - General]<o:p></o:p></span></p>
<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal"><span style="color:black"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> Lu, Victor Cheng Chi (Victor) <<a href="mailto:VictorChengChi.Lu@amd.com">VictorChengChi.Lu@amd.com</a>><br>
<b>Sent:</b> Tuesday, January 2, 2024 12:30 PM<br>
<b>To:</b> <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>><br>
<b>Cc:</b> Chander, Vignesh <<a href="mailto:Vignesh.Chander@amd.com">Vignesh.Chander@amd.com</a>>; Lu, Victor Cheng Chi (Victor) <<a href="mailto:VictorChengChi.Lu@amd.com">VictorChengChi.Lu@amd.com</a>><br>
<b>Subject:</b> [PATCH 3/4] drm/amdgpu: Use correct SRIOV macro for gmc_v9_0_vm_fault_interrupt_state</span>
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<p class="MsoNormal"> <o:p></o:p></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt">Under SRIOV, programming to VM_CONTEXT*_CNTL regs failed because the<br>
current macro does not pass through the correct xcc instance.<br>
Use the *REG32_XCC macro in this case.<br>
<br>
The behaviour without SRIOV is the same.<br>
<br>
Signed-off-by: Victor Lu <<a href="mailto:victorchengchi.lu@amd.com">victorchengchi.lu@amd.com</a>><br>
---<br>
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++----<br>
1 file changed, 4 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
index 473a774294ce..e2e14d40109c 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c<br>
@@ -496,14 +496,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,<br>
if (j >= AMDGPU_MMHUB0(0))<br>
tmp = RREG32_SOC15_IP(MMHUB, reg);<br>
else<br>
- tmp = RREG32_SOC15_IP(GC, reg);<br>
+ tmp = RREG32_XCC(reg, j);<br>
<br>
tmp &= ~bits;<br>
<br>
if (j >= AMDGPU_MMHUB0(0))<br>
WREG32_SOC15_IP(MMHUB, reg, tmp);<br>
else<br>
- WREG32_SOC15_IP(GC, reg, tmp);<br>
+ WREG32_XCC(reg, tmp, j);<br>
}<br>
}<br>
break;<br>
@@ -524,14 +524,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,<br>
if (j >= AMDGPU_MMHUB0(0))<br>
tmp = RREG32_SOC15_IP(MMHUB, reg);<br>
else<br>
- tmp = RREG32_SOC15_IP(GC, reg);<br>
+ tmp = RREG32_XCC(reg, j);<br>
<br>
tmp |= bits;<br>
<br>
if (j >= AMDGPU_MMHUB0(0))<br>
WREG32_SOC15_IP(MMHUB, reg, tmp);<br>
else<br>
- WREG32_SOC15_IP(GC, reg, tmp);<br>
+ WREG32_XCC(reg, tmp, j);<br>
}<br>
}<br>
break;<br>
-- <br>
2.34.1<o:p></o:p></p>
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