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[Public]<br>
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Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com></div>
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Regards,</div>
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Nicholas Kazlauskas</div>
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<b>From:</b> Mahfooz, Hamza <Hamza.Mahfooz@amd.com><br>
<b>Sent:</b> Friday, March 22, 2024 2:56 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>; Li, Roman <Roman.Li@amd.com>; Li, Sun peng (Leo) <Sunpeng.Li@amd.com>; Wentland, Harry <Harry.Wentland@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Limonciello, Mario <Mario.Limonciello@amd.com>;
Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Mahfooz, Hamza <Hamza.Mahfooz@amd.com>; Broadworth, Mark <Mark.Broadworth@amd.com><br>
<b>Subject:</b> [PATCH] drm/amd/display: fix IPX enablement</div>
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<div style="font-size: 11pt;">We need to re-enable idle power optimizations after entering PSR. Since,<br>
we get kicked out of idle power optimizations before entering PSR<br>
(entering PSR requires us to write to DCN registers, which isn't allowed<br>
while we are in IPS).<br>
<br>
Fixes: bfe4f0b0e717 ("drm/amd/display: Add more checks for exiting idle in DC")<br>
Tested-by: Mark Broadworth <mark.broadworth@amd.com><br>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com><br>
---<br>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 +++++---<br>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h | 2 +-<br>
2 files changed, 6 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c<br>
index a48a79e84e82..bfa090432ce2 100644<br>
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c<br>
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c<br>
@@ -141,9 +141,8 @@ bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)<br>
* amdgpu_dm_psr_enable() - enable psr f/w<br>
* @stream: stream state<br>
*<br>
- * Return: true if success<br>
*/<br>
-bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)<br>
+void amdgpu_dm_psr_enable(struct dc_stream_state *stream)<br>
{<br>
struct dc_link *link = stream->link;<br>
unsigned int vsync_rate_hz = 0;<br>
@@ -190,7 +189,10 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream)<br>
if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)<br>
power_opt |= psr_power_opt_z10_static_screen;<br>
<br>
- return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);<br>
+ dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);<br>
+<br>
+ if (link->ctx->dc->caps.ips_support)<br>
+ dc_allow_idle_optimizations(link->ctx->dc, true);<br>
}<br>
<br>
/*<br>
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h<br>
index 6806b3c9c84b..1fdfd183c0d9 100644<br>
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h<br>
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h<br>
@@ -32,7 +32,7 @@<br>
#define AMDGPU_DM_PSR_ENTRY_DELAY 5<br>
<br>
void amdgpu_dm_set_psr_caps(struct dc_link *link);<br>
-bool amdgpu_dm_psr_enable(struct dc_stream_state *stream);<br>
+void amdgpu_dm_psr_enable(struct dc_stream_state *stream);<br>
bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);<br>
bool amdgpu_dm_psr_disable(struct dc_stream_state *stream);<br>
bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);<br>
--<br>
2.44.0<br>
<br>
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