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[AMD Official Use Only - General]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Lazar, Lijo <Lijo.Lazar@amd.com><br>
<b>Sent:</b> Wednesday, March 27, 2024 10:05 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Zhang, Hawking <Hawking.Zhang@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhu, James <James.Zhu@amd.com>; Kamal, Asad <Asad.Kamal@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdgpu: Fix VCN allocation in CPX partition</font>
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<div class="PlainText">VCN need not be shared in CPX mode always for all GFX 9.4.3 SOC SKUs. In<br>
certain configs, VCN instance can be exclusively allocated to a<br>
partition even under CPX mode.<br>
<br>
Signed-off-by: Lijo Lazar <lijo.lazar@amd.com><br>
Reviewed-by: James Zhu <James.Zhu@amd.com><br>
Reviewed-by: Asad Kamal <asad.kamal@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 15 +++++++++++----<br>
1 file changed, 11 insertions(+), 4 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c<br>
index d6f808acfb17..fbb43ae7624f 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c<br>
@@ -62,6 +62,11 @@ void aqua_vanjaram_doorbell_index_init(struct amdgpu_device *adev)<br>
adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_LAYOUT1_MAX_ASSIGNMENT << 1;<br>
}<br>
<br>
+static bool aqua_vanjaram_xcp_vcn_shared(struct amdgpu_device *adev)<br>
+{<br>
+ return (adev->xcp_mgr->num_xcps > adev->vcn.num_vcn_inst);<br>
+}<br>
+<br>
static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,<br>
uint32_t inst_idx, struct amdgpu_ring *ring)<br>
{<br>
@@ -87,7 +92,7 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev,<br>
case AMDGPU_RING_TYPE_VCN_ENC:<br>
case AMDGPU_RING_TYPE_VCN_JPEG:<br>
ip_blk = AMDGPU_XCP_VCN;<br>
- if (adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)<br>
+ if (aqua_vanjaram_xcp_vcn_shared(adev))<br>
inst_mask = 1 << (inst_idx * 2);<br>
break;<br>
default:<br>
@@ -140,10 +145,12 @@ static int aqua_vanjaram_xcp_sched_list_update(<br>
<br>
aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id);<br>
<br>
- /* VCN is shared by two partitions under CPX MODE */<br>
+ /* VCN may be shared by two partitions under CPX MODE in certain<br>
+ * configs.<br>
+ */<br>
if ((ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC ||<br>
- ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&<br>
- adev->xcp_mgr->mode == AMDGPU_CPX_PARTITION_MODE)<br>
+ ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) &&<br>
+ aqua_vanjaram_xcp_vcn_shared(adev))<br>
aqua_vanjaram_xcp_gpu_sched_update(adev, ring, ring->xcp_id + 1);<br>
}<br>
<br>
-- <br>
2.25.1<br>
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