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<div class="moz-cite-prefix">On 4/16/2024 7:30 PM, Christian König
wrote:<br>
</div>
<blockquote type="cite" cite="mid:526b2e61-006e-4bc7-abaf-afa3f6a0af81@amd.com">Am
16.04.24 um 15:55 schrieb Alex Deucher:
<br>
<blockquote type="cite">On Tue, Apr 16, 2024 at 8:08 AM Sunil
Khatri <a class="moz-txt-link-rfc2396E" href="mailto:sunil.khatri@amd.com"><sunil.khatri@amd.com></a> wrote:
<br>
<blockquote type="cite">Adding gfx10 gc registers to be used for
register
<br>
dump via devcoredump during a gpu reset.
<br>
<br>
Signed-off-by: Sunil Khatri <a class="moz-txt-link-rfc2396E" href="mailto:sunil.khatri@amd.com"><sunil.khatri@amd.com></a>
<br>
---
<br>
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ++
<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 +
<br>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 131
+++++++++++++++++-
<br>
.../include/asic_reg/gc/gc_10_1_0_offset.h | 12 ++
<br>
4 files changed, 158 insertions(+), 1 deletion(-)
<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
<br>
index e0d7f4ee7e16..e016ac33629d 100644
<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
<br>
@@ -139,6 +139,18 @@ enum amdgpu_ss {
<br>
AMDGPU_SS_DRV_UNLOAD
<br>
};
<br>
<br>
+struct hwip_reg_entry {
<br>
+ u32 hwip;
<br>
+ u32 inst;
<br>
+ u32 seg;
<br>
+ u32 reg_offset;
<br>
+};
<br>
+
<br>
+struct reg_pair {
<br>
+ u32 offset;
<br>
+ u32 value;
<br>
+};
<br>
+
<br>
struct amdgpu_watchdog_timer {
<br>
bool timeout_fatal_disable;
<br>
uint32_t period; /* maxCycles = (1 << period),
the number of cycles before a timeout */
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
<br>
index 04a86dff71e6..295a2c8d2e48 100644
<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
<br>
@@ -433,6 +433,10 @@ struct amdgpu_gfx {
<br>
uint32_t num_xcc_per_xcp;
<br>
struct mutex partition_mutex;
<br>
bool mcbp; /* mid command
buffer preemption */
<br>
+
<br>
+ /* IP reg dump */
<br>
+ struct reg_pair *ip_dump;
<br>
+ uint32_t reg_count;
<br>
};
<br>
<br>
struct amdgpu_gfx_ras_reg_entry {
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
<br>
index a0bc4196ff8b..46e136609ff1 100644
<br>
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
<br>
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
<br>
@@ -276,6 +276,99 @@
MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
<br>
MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
<br>
MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
<br>
<br>
+static const struct hwip_reg_entry gc_reg_list_10_1[] = {
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS3) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_BUSY_STAT) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT2) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT2) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_GFX_ERROR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_GFX_HPD_STATUS0) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB_BASE) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB_RPTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB_WPTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB0_BASE) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB0_RPTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB0_WPTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB1_BASE) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB1_RPTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB1_WPTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB2_BASE) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB2_WPTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_RB2_WPTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB1_CMD_BUFSZ) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB2_CMD_BUFSZ) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_IB1_CMD_BUFSZ) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_IB2_CMD_BUFSZ) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB1_BASE_LO) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB1_BASE_HI) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB1_BUFSZ) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB2_BASE_LO) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB2_BASE_HI) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_IB2_BUFSZ) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_IB1_BASE_LO) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_IB1_BASE_HI) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_IB1_BUFSZ) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_IB2_BASE_LO) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_IB2_BASE_HI) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_IB2_BUFSZ) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCPF_UTCL1_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCPC_UTCL1_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCPG_UTCL1_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmGDS_PROTECTION_FAULT) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmGDS_VM_PROTECTION_FAULT) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmIA_UTCL1_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmIA_UTCL1_STATUS_2) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmPA_CL_CNTL_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_UTCL1_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRMI_UTCL1_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmSQC_DCACHE_UTCL0_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmSQC_ICACHE_UTCL0_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmSQG_UTCL0_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmTCP_UTCL0_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmWD_UTCL1_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0,
mmGCVM_L2_PROTECTION_FAULT_CNTL) },
<br>
+ { SOC15_REG_ENTRY(GC, 0,
mmGCVM_L2_PROTECTION_FAULT_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_DEBUG) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_MEC_CNTL) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_MES_CNTL) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CE_INSTR_PNTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_MEC1_INSTR_PNTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_MEC2_INSTR_PNTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0,
mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_MES_INSTR_PNTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_ME_INSTR_PNTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_PFP_INSTR_PNTR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_STAT) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SMU_COMMAND) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SMU_MESSAGE) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SMU_ARGUMENT_1) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SMU_ARGUMENT_2) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SMU_ARGUMENT_3) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SMU_ARGUMENT_4) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmSMU_RLC_RESPONSE) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SAFE_MODE) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SMU_SAFE_MODE) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_RLCS_GPM_STAT_2) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_SPP_STATUS) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS)
},
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_INT_STAT) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_GENERAL_6) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_DEBUG_INST_A) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_DEBUG_INST_B) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_GPM_DEBUG_INST_ADDR) },
<br>
+ { SOC15_REG_ENTRY(GC, 0, mmRLC_LX6_CORE_PDEBUG_INST) }
<br>
+};
<br>
</blockquote>
Might want to add the string name for the register as well.
<br>
</blockquote>
<br>
I think we could hack up the SOC15_REG_ENTRY() macro for that.
E.g. have a const pointer to the stringified last parameter in the
hwip_reg_entry.
<br>
</blockquote>
<p><br>
</p>
<div style="color: #cccccc;background-color: #1f1f1f;font-family: Consolas, 'Courier New', monospace;font-weight: normal;font-size: 14px;line-height: 19px;white-space: pre;"><div><span style="color: #569cd6;">How does this sound ?
</span></div><div><span style="color: #569cd6;">struct</span><span style="color: #cccccc;"> </span><span style="color: #4ec9b0;">amdgpu_hwip_reg_entry</span><span style="color: #cccccc;"> {</span></div><div><span style="color: #cccccc;"> u32 </span><span style="color: #9cdcfe;">hwip</span><span style="color: #cccccc;">;</span></div><div><span style="color: #cccccc;"> u32 </span><span style="color: #9cdcfe;">inst</span><span style="color: #cccccc;">;</span></div><div><span style="color: #cccccc;"> u32 </span><span style="color: #9cdcfe;">seg</span><span style="color: #cccccc;">;</span></div><div><span style="color: #cccccc;"> u32 </span><span style="color: #9cdcfe;">reg_offset</span><span style="color: #cccccc;">;</span></div><div><span style="color: #cccccc;"> </span><span style="color: #569cd6;">char</span><span style="color: #cccccc;"> </span><span style="color: #9cdcfe;">reg_name</span><span style="color: #cccccc;">[</span><span style="color: #b5cea8;">50</span><span style="color: #cccccc;">];</span></div><div><span style="color: #cccccc;">};</span></div></div>
<p></p>
<div style="color: #cccccc;background-color: #1f1f1f;font-family: Consolas, 'Courier New', monospace;font-weight: normal;font-size: 14px;line-height: 19px;white-space: pre;"><div><span style="color: #c586c0;">#define</span><span style="color: #569cd6;"> </span><span style="color: #569cd6;">SOC15_REG_ENTRY</span><span style="color: #569cd6;">_STR(</span><span style="color: #9cdcfe;">ip</span><span style="color: #569cd6;">, </span><span style="color: #9cdcfe;">inst</span><span style="color: #569cd6;">, </span><span style="color: #9cdcfe;">reg</span><span style="color: #569cd6;">) ip##_HWIP, inst, reg##_BASE_IDX, reg, #reg</span></div><div><div style="color: #cccccc;background-color: #1f1f1f;font-family: Consolas, 'Courier New', monospace;font-weight: normal;font-size: 14px;line-height: 19px;white-space: pre;"><div><span style="color: #569cd6;">static</span><span style="color: #cccccc;"> </span><span style="color: #569cd6;">const</span><span style="color: #cccccc;"> </span><span style="color: #569cd6;">struct</span><span style="color: #cccccc;"> </span><span style="color: #4ec9b0;">amdgpu_hwip_reg_entry</span><span style="color: #cccccc;"> </span><span style="color: #9cdcfe;">gc_reg_list_10_1</span><span style="color: #569cd6;">[]</span><span style="color: #cccccc;"> </span><span style="color: #d4d4d4;">=</span><span style="color: #cccccc;"> {</span></div><div><span style="color: #cccccc;"> { </span><span style="color: #569cd6;">SOC15_REG_ENTRY_STR</span><span style="color: #cccccc;">(GC, </span><span style="color: #b5cea8;">0</span><span style="color: #cccccc;">, </span><span style="color: #569cd6;">mmGRBM_STATUS</span><span style="color: #cccccc;">) },</span></div><div><span style="color: #cccccc;">}
</span></div></div></div></div>
<br>
<br>
<blockquote type="cite" cite="mid:526b2e61-006e-4bc7-abaf-afa3f6a0af81@amd.com">
<br>
And btw please name that amdgpu_hwip_reg_entry.
<br>
</blockquote>
Noted<br>
<blockquote type="cite" cite="mid:526b2e61-006e-4bc7-abaf-afa3f6a0af81@amd.com">
<br>
Regards,
<br>
Christian.
<br>
<br>
<blockquote type="cite"> It would
<br>
be nice to print the register name rather than the offset in the
<br>
devcoredump.
<br>
<br>
E.g.,
<br>
<br>
<br>
<blockquote type="cite">+
<br>
static const struct soc15_reg_golden
golden_settings_gc_10_1[] = {
<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4,
0xffffffff, 0x00400014),
<br>
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL,
0xfcff8fff, 0xf8000100),
<br>
@@ -4490,6 +4583,23 @@ static int
gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int
ring_id,
<br>
hw_prio, NULL);
<br>
}
<br>
<br>
+static void gfx_v10_0_alloc_dump_mem(struct amdgpu_device
*adev)
<br>
+{
<br>
+ uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
<br>
+ struct reg_pair *ptr;
<br>
+
<br>
+ ptr = kcalloc(reg_count, sizeof(struct reg_pair),
GFP_KERNEL);
<br>
</blockquote>
I think you only need to allocate enough memory to store the
register
<br>
values. We already have the offsets in the array above.
<br>
{ SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS), "mmGRBM_STATUS" },
<br>
<br>
<blockquote type="cite">+ if (ptr == NULL) {
<br>
+ DRM_ERROR("Failed to allocate memory for IP
Dump\n");
<br>
+ adev->gfx.ip_dump = NULL;
<br>
+ adev->gfx.reg_count = 0;
<br>
+ }
<br>
+ else {
<br>
+ adev->gfx.ip_dump = ptr;
<br>
+ adev->gfx.reg_count = reg_count;
<br>
+ }
<br>
+}
<br>
+
<br>
static int gfx_v10_0_sw_init(void *handle)
<br>
{
<br>
int i, j, k, r, ring_id = 0;
<br>
@@ -4642,6 +4752,8 @@ static int gfx_v10_0_sw_init(void
*handle)
<br>
<br>
gfx_v10_0_gpu_early_init(adev);
<br>
<br>
+ gfx_v10_0_alloc_dump_mem(adev);
<br>
+
<br>
return 0;
<br>
}
<br>
<br>
@@ -4694,6 +4806,8 @@ static int gfx_v10_0_sw_fini(void
*handle)
<br>
<br>
gfx_v10_0_free_microcode(adev);
<br>
<br>
+ kfree(adev->gfx.ip_dump);
<br>
+
<br>
return 0;
<br>
}
<br>
<br>
@@ -9154,6 +9268,21 @@ static void
gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
<br>
amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
<br>
}
<br>
<br>
+static void gfx_v10_ip_dump(void *handle)
<br>
+{
<br>
+ struct amdgpu_device *adev = (struct amdgpu_device
*)handle;
<br>
+ uint32_t i;
<br>
+ uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1);
<br>
+
<br>
+ if (!adev->gfx.ip_dump)
<br>
+ return;
<br>
+
<br>
</blockquote>
Need turn disallow gfxoff before reading the gfx registers:
<br>
<br>
amdgpu_gfx_off_ctrl(adev, false);
<br>
<br>
<blockquote type="cite">+ for (i = 0; i < reg_count;
i++) {
<br>
+ adev->gfx.ip_dump[i].offset =
gc_reg_list_10_1[i].reg_offset;
<br>
</blockquote>
No need to store the offset. We already have it in the static
array above.
<br>
<br>
<blockquote type="cite">+
adev->gfx.ip_dump[i].value =
RREG32(SOC15_REG_ENTRY_OFFSET(gc_reg_list_10_1[i]));
<br>
+ }
<br>
</blockquote>
And then allow it again:
<br>
<br>
amdgpu_gfx_off_ctrl(adev, true);
<br>
<br>
<blockquote type="cite">+}
<br>
+
<br>
static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
<br>
.name = "gfx_v10_0",
<br>
.early_init = gfx_v10_0_early_init,
<br>
@@ -9170,7 +9299,7 @@ static const struct amd_ip_funcs
gfx_v10_0_ip_funcs = {
<br>
.set_clockgating_state =
gfx_v10_0_set_clockgating_state,
<br>
.set_powergating_state =
gfx_v10_0_set_powergating_state,
<br>
.get_clockgating_state =
gfx_v10_0_get_clockgating_state,
<br>
- .dump_ip_state = NULL,
<br>
+ .dump_ip_state = gfx_v10_ip_dump,
<br>
};
<br>
<br>
static const struct amdgpu_ring_funcs
gfx_v10_0_ring_funcs_gfx = {
<br>
diff --git
a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
<br>
index 4908044f7409..4c8e7fdb6976 100644
<br>
---
a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
<br>
+++
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
<br>
@@ -4830,6 +4830,8 @@
<br>
#define
mmCP_ECC_FIRSTOCCURRENCE_RING2_BASE_IDX
0
<br>
#define
mmGB_EDC_MODE
0x1e1e
<br>
#define
mmGB_EDC_MODE_BASE_IDX
0
<br>
+#define
mmCP_DEBUG
0x1e1f
<br>
+#define
mmCP_DEBUG_BASE_IDX
0
<br>
#define
mmCP_FETCHER_SOURCE
0x1e22
<br>
#define
mmCP_FETCHER_SOURCE_BASE_IDX
0
<br>
#define
mmCP_PQ_WPTR_POLL_CNTL
0x1e23
<br>
@@ -7778,6 +7780,8 @@
<br>
#define
mmCP_MES_DOORBELL_CONTROL5_BASE_IDX
1
<br>
#define
mmCP_MES_DOORBELL_CONTROL6
0x2841
<br>
#define
mmCP_MES_DOORBELL_CONTROL6_BASE_IDX
1
<br>
+#define
mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR
0x2842
<br>
+#define
mmCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX
1
<br>
#define
mmCP_MES_GP0_LO
0x2843
<br>
#define
mmCP_MES_GP0_LO_BASE_IDX
1
<br>
#define
mmCP_MES_GP0_HI
0x2844
<br>
@@ -9332,10 +9336,16 @@
<br>
#define
mmRLC_LB_CNTR_INIT_1_BASE_IDX
1
<br>
#define
mmRLC_LB_CNTR_1
0x4c1c
<br>
#define
mmRLC_LB_CNTR_1_BASE_IDX
1
<br>
+#define
mmRLC_GPM_DEBUG_INST_ADDR
0x4c1d
<br>
+#define
mmRLC_GPM_DEBUG_INST_ADDR_BASE_IDX
1
<br>
#define
mmRLC_JUMP_TABLE_RESTORE
0x4c1e
<br>
#define
mmRLC_JUMP_TABLE_RESTORE_BASE_IDX
1
<br>
#define
mmRLC_PG_DELAY_2
0x4c1f
<br>
#define
mmRLC_PG_DELAY_2_BASE_IDX
1
<br>
+#define
mmRLC_GPM_DEBUG_INST_A
0x4c22
<br>
+#define
mmRLC_GPM_DEBUG_INST_A_BASE_IDX
1
<br>
+#define
mmRLC_GPM_DEBUG_INST_B
0x4c23
<br>
+#define
mmRLC_GPM_DEBUG_INST_B_BASE_IDX
1
<br>
#define
mmRLC_GPU_CLOCK_COUNT_LSB
0x4c24
<br>
#define
mmRLC_GPU_CLOCK_COUNT_LSB_BASE_IDX
1
<br>
#define
mmRLC_GPU_CLOCK_COUNT_MSB
0x4c25
<br>
@@ -9720,6 +9730,8 @@
<br>
#define
mmRLC_SPM_THREAD_TRACE_CTRL_BASE_IDX
1
<br>
#define
mmRLC_LB_CNTR_2
0x4de7
<br>
#define
mmRLC_LB_CNTR_2_BASE_IDX
1
<br>
+#define
mmRLC_LX6_CORE_PDEBUG_INST
0x4deb
<br>
+#define
mmRLC_LX6_CORE_PDEBUG_INST_BASE_IDX
1
<br>
#define
mmRLC_CPAXI_DOORBELL_MON_CTRL
0x4df1
<br>
#define
mmRLC_CPAXI_DOORBELL_MON_CTRL_BASE_IDX
1
<br>
#define
mmRLC_CPAXI_DOORBELL_MON_STAT
0x4df2
<br>
--
<br>
2.34.1
<br>
<br>
</blockquote>
</blockquote>
<br>
</blockquote>
</body>
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