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[AMD Official Use Only - General]<br>
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<div dir="ltr">Series is</div>
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<div dir="ltr">Acked-by: Yang Wang<kevinyang.wang@amd.com></div>
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<div dir="ltr">Best Regards,</div>
<div dir="ltr">Kevin </div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif"><b>From:</b> Ma, Jun <Jun.Ma2@amd.com><br>
<b>Sent:</b> Friday, May 10, 2024 17:42<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Feng, Kenneth <Kenneth.Feng@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Wang, Yang(Kevin) <KevinYang.Wang@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Ma, Jun <Jun.Ma2@amd.com><br>
<b>Subject:</b> [PATCH 3/3] drm/amdgpu/pm: Fix the null pointer dereference in apply_state_adjust_rules
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<div class="PlainText">Check the pointer value to fix potential null pointer<br>
dereference<br>
<br>
Signed-off-by: Ma Jun <Jun.Ma2@amd.com><br>
---<br>
.../gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c | 7 +++++--<br>
.../gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c | 14 ++++++++------<br>
.../gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c | 7 +++++--<br>
3 files changed, 18 insertions(+), 10 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c<br>
index 9301e65ff13c..632a25957477 100644<br>
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c<br>
@@ -3314,8 +3314,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,<br>
const struct pp_power_state *current_ps)<br>
{<br>
struct amdgpu_device *adev = hwmgr->adev;<br>
- struct smu7_power_state *smu7_ps =<br>
- cast_phw_smu7_power_state(&request_ps->hardware);<br>
+ struct smu7_power_state *smu7_ps;<br>
uint32_t sclk;<br>
uint32_t mclk;<br>
struct PP_Clocks minimum_clocks = {0};<br>
@@ -3332,6 +3331,10 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,<br>
uint32_t latency;<br>
bool latency_allowed = false;<br>
<br>
+ smu7_ps = cast_phw_smu7_power_state(&request_ps->hardware);<br>
+ if (!smu7_ps)<br>
+ return -EINVAL;<br>
+<br>
data->battery_state = (PP_StateUILabel_Battery ==<br>
request_ps->classification.ui_label);<br>
data->mclk_ignore_signal = false;<br>
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c<br>
index b858cc2a5c9e..7e1197420873 100644<br>
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu8_hwmgr.c<br>
@@ -1074,16 +1074,18 @@ static int smu8_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,<br>
struct pp_power_state *prequest_ps,<br>
const struct pp_power_state *pcurrent_ps)<br>
{<br>
- struct smu8_power_state *smu8_ps =<br>
- cast_smu8_power_state(&prequest_ps->hardware);<br>
-<br>
- const struct smu8_power_state *smu8_current_ps =<br>
- cast_const_smu8_power_state(&pcurrent_ps->hardware);<br>
-<br>
+ struct smu8_power_state *smu8_ps;<br>
+ const struct smu8_power_state *smu8_current_ps;<br>
struct smu8_hwmgr *data = hwmgr->backend;<br>
struct PP_Clocks clocks = {0, 0, 0, 0};<br>
bool force_high;<br>
<br>
+ smu8_ps = cast_smu8_power_state(&prequest_ps->hardware);<br>
+ smu8_current_ps = cast_const_smu8_power_state(&pcurrent_ps->hardware);<br>
+<br>
+ if (!smu8_ps || !smu8_current_ps)<br>
+ return -EINVAL;<br>
+<br>
smu8_ps->need_dfs_bypass = true;<br>
<br>
data->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);<br>
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c<br>
index 3b461c07344b..6524d99e5cab 100644<br>
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c<br>
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_hwmgr.c<br>
@@ -3280,8 +3280,7 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,<br>
const struct pp_power_state *current_ps)<br>
{<br>
struct amdgpu_device *adev = hwmgr->adev;<br>
- struct vega10_power_state *vega10_ps =<br>
- cast_phw_vega10_power_state(&request_ps->hardware);<br>
+ struct vega10_power_state *vega10_ps;<br>
uint32_t sclk;<br>
uint32_t mclk;<br>
struct PP_Clocks minimum_clocks = {0};<br>
@@ -3299,6 +3298,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,<br>
uint32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0;<br>
uint32_t latency;<br>
<br>
+ vega10_ps = cast_phw_vega10_power_state(&request_ps->hardware);<br>
+ if (!vega10_ps)<br>
+ return -EINVAL;<br>
+<br>
data->battery_state = (PP_StateUILabel_Battery ==<br>
request_ps->classification.ui_label);<br>
<br>
-- <br>
2.34.1<br>
<br>
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