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[AMD Official Use Only - AMD Internal Distribution Only]<br>
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<div dir="auto">Never mind, bit 16 and above is probably because of dword aligned offset.</div>
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<div dir="auto">Any reason not to do this in kiq/rlc based writes to normalise all?</div>
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<div dir="auto">Thanks,</div>
<div dir="auto">Lijo</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Lazar, Lijo<br>
<b>Sent:</b> Friday, June 14, 2024 5:20:30 PM<br>
<b>To:</b> Jian, Jane <Jane.Jian@amd.com>; Chang, HaiJun <HaiJun.Chang@amd.com>; Zhao, Victor <Victor.Zhao@amd.com><br>
<b>Cc:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu: keep init xcc0 for all xccs under sriov</font>
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On 6/14/2024 4:40 PM, Jane Jian wrote:<br>
> [WHY]<br>
> sriov has the higher bit violation when flushing tlb<br>
> <br>
> [HOW]<br>
> for sriov only init XCC0(lower 16-bit) for all XCCs to avoid higher bit violation<br>
> since kiq ring is always local, local address without XCC ID is enough to be sent to the XCC KIQ<br>
> <br>
<br>
The description is incorrect.<br>
<br>
Bits 18:20 represent xcc id. To guarantee all paths pass a local<br>
address, you should just strip bits 18:20 in kiq/rlcg read/write<br>
functions rather than here.<br>
<br>
Thanks,<br>
Lijo<br>
<br>
> Signed-off-by: Jane Jian <Jane.Jian@amd.com><br>
> ---<br>
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 23 +++++++++++++++--------<br>
> 1 file changed, 15 insertions(+), 8 deletions(-)<br>
> <br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c<br>
> index e14acab5cceb..4e38a66a52f4 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c<br>
> @@ -537,29 +537,36 @@ static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask)<br>
> {<br>
> struct amdgpu_vmhub *hub;<br>
> int i;<br>
> + uint32_t gc_index;<br>
> <br>
> for_each_inst(i, xcc_mask) {<br>
> hub = &adev->vmhub[AMDGPU_GFXHUB(i)];<br>
> <br>
> + /* for sriov only init XCC0(lower 16-bit) to avoid higher bit violation */<br>
> + if (amdgpu_sriov_vf(adev))<br>
> + gc_index = 0;<br>
> + else<br>
> + gc_index = GET_INST(GC, i);<br>
> +<br>
> hub->ctx0_ptb_addr_lo32 =<br>
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i),<br>
> + SOC15_REG_OFFSET(GC, gc_index,<br>
> regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);<br>
> hub->ctx0_ptb_addr_hi32 =<br>
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i),<br>
> + SOC15_REG_OFFSET(GC, gc_index,<br>
> regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);<br>
> hub->vm_inv_eng0_sem =<br>
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM);<br>
> + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_SEM);<br>
> hub->vm_inv_eng0_req =<br>
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ);<br>
> + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_REQ);<br>
> hub->vm_inv_eng0_ack =<br>
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK);<br>
> + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_ACK);<br>
> hub->vm_context0_cntl =<br>
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL);<br>
> + SOC15_REG_OFFSET(GC, gc_index, regVM_CONTEXT0_CNTL);<br>
> hub->vm_l2_pro_fault_status =<br>
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i),<br>
> + SOC15_REG_OFFSET(GC, gc_index,<br>
> regVM_L2_PROTECTION_FAULT_STATUS);<br>
> hub->vm_l2_pro_fault_cntl =<br>
> - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL);<br>
> + SOC15_REG_OFFSET(GC, gc_index, regVM_L2_PROTECTION_FAULT_CNTL);<br>
> <br>
> hub->ctx_distance = regVM_CONTEXT1_CNTL -<br>
> regVM_CONTEXT0_CNTL;<br>
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