<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=us-ascii"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="#467886" vlink="#96607D" style="word-wrap:break-word"> [AMD Official Use Only - AMD Internal Distribution Only] <div> <div class="WordSection1"> Hi Lijo,<o:p></o:p> <o:p> </o:p> Right, 18bits are byte aligned range of local XCC register, 16bites are dword aligned offset range<o:p></o:p> <o:p> </o:p> We find the normalization needs to be applied to many functions, like<o:p></o:p> <ul style="margin-top:0in" type="disc"> <li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">KIQ: amdgpu_kiq_r/wreg/ <o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">RLC: amdgpu_virt_rlcg_reg_rw<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">KIQ: amdgpu_gmc_fw_reg_write_reg_wait<o:p></o:p></li><li class="MsoListParagraph" style="margin-left:0in;mso-list:l0 level1 lfo1">KIQ: amdgpu_ring_emit_reg_write_reg_wait/amdgpu_ring_emit_reg_wait/amdgpu_ring_emit_wreg<o:p></o:p></li></ul> <o:p> </o:p> For sriov gfx register access, it only has 2 ways: rlc or kiq. Both of the ways can use local xcc offset, so we think it’s simpler change to init the gfx register offsets with local xcc offset only.<o:p></o:p> <o:p> </o:p> Thanks,<o:p></o:p> HaiJun<o:p></o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Lazar, Lijo <Lijo.Lazar@amd.com> Sent: Saturday, June 15, 2024 10:09 AM To: Jian, Jane <Jane.Jian@amd.com>; Chang, HaiJun <HaiJun.Chang@amd.com>; Zhao, Victor <Victor.Zhao@amd.com> Cc: amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: keep init xcc0 for all xccs under sriov<o:p></o:p> </div> </div> <o:p> </o:p> [AMD Official Use Only - AMD Internal Distribution Only]<o:p></o:p> <o:p> </o:p> <div> <div> Never mind, bit 16 and above is probably because of dword aligned offset.<o:p></o:p> </div> <div> <o:p> </o:p> </div> <div> Any reason not to do this in kiq/rlc based writes to normalise all?<o:p></o:p> </div> <div id="ms-outlook-mobile-signature"> <div> <o:p> </o:p> </div> <div> Thanks,<o:p></o:p> </div> <div> Lijo<o:p></o:p> </div> </div> <div class="MsoNormal" align="center" style="text-align:center"> <hr size="2" width="98%" align="center"> </div> <div id="divRplyFwdMsg"> From: Lazar, Lijo Sent: Friday, June 14, 2024 5:20:30 PM To: Jian, Jane <<a href="mailto:Jane.Jian@amd.com">Jane.Jian@amd.com</a>>; Chang, HaiJun <<a href="mailto:HaiJun.Chang@amd.com">HaiJun.Chang@amd.com</a>>; Zhao, Victor <<a href="mailto:Victor.Zhao@amd.com">Victor.Zhao@amd.com</a>> Cc: <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> <<a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>> Subject: Re: [PATCH] drm/amdgpu: keep init xcc0 for all xccs under sriov <o:p></o:p> <div> <o:p></o:p> </div> </div> <div> <div> On 6/14/2024 4:40 PM, Jane Jian wrote: > [WHY] > sriov has the higher bit violation when flushing tlb > > [HOW] > for sriov only init XCC0(lower 16-bit) for all XCCs to avoid higher bit violation > since kiq ring is always local, local address without XCC ID is enough to be sent to the XCC KIQ > The description is incorrect. Bits 18:20 represent xcc id. To guarantee all paths pass a local address, you should just strip bits 18:20 in kiq/rlcg read/write functions rather than here. Thanks, Lijo > Signed-off-by: Jane Jian <<a href="mailto:Jane.Jian@amd.com">Jane.Jian@amd.com</a>> > --- > drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 23 +++++++++++++++-------- > 1 file changed, 15 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > index e14acab5cceb..4e38a66a52f4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c > @@ -537,29 +537,36 @@ static void gfxhub_v1_2_xcc_init(struct amdgpu_device *adev, uint32_t xcc_mask) > { > struct amdgpu_vmhub *hub; > int i; > + uint32_t gc_index; > > for_each_inst(i, xcc_mask) { > hub = &adev->vmhub[AMDGPU_GFXHUB(i)]; > > + /* for sriov only init XCC0(lower 16-bit) to avoid higher bit violation */ > + if (amdgpu_sriov_vf(adev)) > + gc_index = 0; > + else > + gc_index = GET_INST(GC, i); > + > hub->ctx0_ptb_addr_lo32 = > - SOC15_REG_OFFSET(GC, GET_INST(GC, i), > + SOC15_REG_OFFSET(GC, gc_index, > regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); > hub->ctx0_ptb_addr_hi32 = > - SOC15_REG_OFFSET(GC, GET_INST(GC, i), > + SOC15_REG_OFFSET(GC, gc_index, > regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); > hub->vm_inv_eng0_sem = > - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_SEM); > + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_SEM); > hub->vm_inv_eng0_req = > - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_REQ); > + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_REQ); > hub->vm_inv_eng0_ack = > - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_INVALIDATE_ENG0_ACK); > + SOC15_REG_OFFSET(GC, gc_index, regVM_INVALIDATE_ENG0_ACK); > hub->vm_context0_cntl = > - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_CONTEXT0_CNTL); > + SOC15_REG_OFFSET(GC, gc_index, regVM_CONTEXT0_CNTL); > hub->vm_l2_pro_fault_status = > - SOC15_REG_OFFSET(GC, GET_INST(GC, i), > + SOC15_REG_OFFSET(GC, gc_index, > regVM_L2_PROTECTION_FAULT_STATUS); > hub->vm_l2_pro_fault_cntl = > - SOC15_REG_OFFSET(GC, GET_INST(GC, i), regVM_L2_PROTECTION_FAULT_CNTL); > + SOC15_REG_OFFSET(GC, gc_index, regVM_L2_PROTECTION_FAULT_CNTL); > > hub->ctx_distance = regVM_CONTEXT1_CNTL - > regVM_CONTEXT0_CNTL;<o:p></o:p> </div> </div> </div> </div> </div> </body> </html>