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[AMD Official Use Only - AMD Internal Distribution Only]<br>
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Reviewed-by: Sreekant Somasekharan <Sreekant.Somasekharan@amd.com></div>
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Regards,</div>
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-Sreekant</div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of David Belanger <david.belanger@amd.com><br>
<b>Sent:</b> Friday, August 23, 2024 7:58 PM<br>
<b>To:</b> amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org><br>
<b>Cc:</b> Belanger, David <David.Belanger@amd.com><br>
<b>Subject:</b> [PATCH] drm/amdkfd: Add cache line size info</font>
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<div class="PlainText">Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding.<br>
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<br>
Populate cache line size info in topology based on information from IP<br>
discovery table.<br>
<br>
Signed-off-by: David Belanger <david.belanger@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 8 +++++++-<br>
1 file changed, 7 insertions(+), 1 deletion(-)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c<br>
index cd7b81b7b939..48caecf7e72e 100644<br>
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c<br>
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c<br>
@@ -1434,7 +1434,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,<br>
pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |<br>
CRAT_CACHE_FLAGS_DATA_CACHE |<br>
CRAT_CACHE_FLAGS_SIMD_CACHE);<br>
- pcache_info[0].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;<br>
+ pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;<br>
+ pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size;<br>
i++;<br>
}<br>
/* Scalar L1 Instruction Cache per SQC */<br>
@@ -1446,6 +1447,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,<br>
CRAT_CACHE_FLAGS_INST_CACHE |<br>
CRAT_CACHE_FLAGS_SIMD_CACHE);<br>
pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;<br>
+ pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size;<br>
i++;<br>
}<br>
/* Scalar L1 Data Cache per SQC */<br>
@@ -1456,6 +1458,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,<br>
CRAT_CACHE_FLAGS_DATA_CACHE |<br>
CRAT_CACHE_FLAGS_SIMD_CACHE);<br>
pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;<br>
+ pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size;<br>
i++;<br>
}<br>
/* GL1 Data Cache per SA */<br>
@@ -1468,6 +1471,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,<br>
CRAT_CACHE_FLAGS_DATA_CACHE |<br>
CRAT_CACHE_FLAGS_SIMD_CACHE);<br>
pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;<br>
+ pcache_info[i].cache_line_size = 0;<br>
i++;<br>
}<br>
/* L2 Data Cache per GPU (Total Tex Cache) */<br>
@@ -1478,6 +1482,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,<br>
CRAT_CACHE_FLAGS_DATA_CACHE |<br>
CRAT_CACHE_FLAGS_SIMD_CACHE);<br>
pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;<br>
+ pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size;<br>
i++;<br>
}<br>
/* L3 Data Cache per GPU */<br>
@@ -1488,6 +1493,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,<br>
CRAT_CACHE_FLAGS_DATA_CACHE |<br>
CRAT_CACHE_FLAGS_SIMD_CACHE);<br>
pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;<br>
+ pcache_info[i].cache_line_size = 0;<br>
i++;<br>
}<br>
return i;<br>
--<br>
2.41.0<br>
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