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    <div class="moz-cite-prefix">On 2024-09-02 05:06, Christian König
      wrote:<br>
    </div>
    <blockquote type="cite" cite="mid:c94ad3ab-669a-4529-96fa-2dbb28791a6c@amd.com">Am
      02.09.24 um 05:03 schrieb Lang Yu:
      <br>
      <blockquote type="cite">Fixes: 5a1c27951966 ("drm/amdgpu:
        implement TLB flush fence")
        <br>
        <br>
        Signed-off-by: Lang Yu <a class="moz-txt-link-rfc2396E" href="mailto:lang.yu@amd.com"><lang.yu@amd.com></a>
        <br>
      </blockquote>
      <br>
      Ah yes, that explains why CPU based updates doesn't work reliable
      any more.
      <br>
    </blockquote>
    <p>My understanding is amdgpu_vm_cpu_commit increase the
      vm->tlb_seq if needs_flush, so this patch only fix the tlb_cb
      memory leaking issue.</p>
    <p>Regards,</p>
    <p>Philip<br>
    </p>
    <blockquote type="cite" cite="mid:c94ad3ab-669a-4529-96fa-2dbb28791a6c@amd.com">
      <br>
      You need to add some explanation to the commit message, e.g.
      something like "CPU based updates doesn't produce a fence."
      <br>
      <br>
      With that done Reviewed-by: Christian König
      <a class="moz-txt-link-rfc2396E" href="mailto:christian.koenig@amd.com"><christian.koenig@amd.com></a>
      <br>
      <br>
      <blockquote type="cite">---
        <br>
          drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++--
        <br>
          1 file changed, 4 insertions(+), 2 deletions(-)
        <br>
        <br>
        diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
        b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
        <br>
        index 1d46a5c81ec4..f93804902fd3 100644
        <br>
        --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
        <br>
        +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
        <br>
        @@ -908,10 +908,12 @@ amdgpu_vm_tlb_flush(struct
        amdgpu_vm_update_params *params,
        <br>
          {
        <br>
              struct amdgpu_vm *vm = params->vm;
        <br>
          -    if (!fence || !*fence)
        <br>
        +    tlb_cb->vm = vm;
        <br>
        +    if (!fence || !*fence) {
        <br>
        +        amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
        <br>
                  return;
        <br>
        +    }
        <br>
          -    tlb_cb->vm = vm;
        <br>
              if (!dma_fence_add_callback(*fence, &tlb_cb->cb,
        <br>
                              amdgpu_vm_tlb_seq_cb)) {
        <br>
                  dma_fence_put(vm->last_tlb_flush);
        <br>
      </blockquote>
      <br>
    </blockquote>
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