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Well that explanation doesn't seem to make much sense either.<br>
<br>
What do you mean with TLB flush is occurring prematurely?<br>
<br>
Regards,<br>
Christian.<br>
<br>
<div class="moz-cite-prefix">Am 05.09.24 um 14:38 schrieb
Andjelkovic, Dejan:<br>
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[AMD Official Use Only - AMD Internal Distribution Only]<br>
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Hi there. We're running into a page fault issue that's very
easily reproducible on a SRIOV environment when using SDMA for
page table updates. Going through mapping logs and trace
files, it seems TLB flush is occurring prematurely. Changing
the usage to KERNEL completely stops the page fault from
occurring with no performance impact, which was confirmed with
extensive testing. Looking through amdgpu_vm_sdma.c, namely
within amdgpu_vm_sdma_update when waiting for PD/PT moves to
be completed, fences are iterated with KERNEL usage specified
which are then added as a job dependency.</div>
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<br>
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Best regards,</div>
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Dejan</div>
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<div id="divRplyFwdMsg" dir="ltr"><font style="font-size:11pt" face="Calibri, sans-serif" color="#000000"><b>From:</b>
Koenig, Christian <a class="moz-txt-link-rfc2396E" href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a><br>
<b>Sent:</b> Thursday, September 5, 2024 1:17 PM<br>
<b>To:</b> Andjelkovic, Dejan
<a class="moz-txt-link-rfc2396E" href="mailto:Dejan.Andjelkovic@amd.com"><Dejan.Andjelkovic@amd.com></a>;
<a class="moz-txt-link-abbreviated" href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a>
<a class="moz-txt-link-rfc2396E" href="mailto:amd-gfx@lists.freedesktop.org"><amd-gfx@lists.freedesktop.org></a><br>
<b>Cc:</b> Prica, Nikola <a class="moz-txt-link-rfc2396E" href="mailto:Nikola.Prica@amd.com"><Nikola.Prica@amd.com></a>;
Kuehling, Felix <a class="moz-txt-link-rfc2396E" href="mailto:Felix.Kuehling@amd.com"><Felix.Kuehling@amd.com></a>; Deng, Emily
<a class="moz-txt-link-rfc2396E" href="mailto:Emily.Deng@amd.com"><Emily.Deng@amd.com></a><br>
<b>Subject:</b> Re: [PATCH] drm/amdgpu: Raise dma resv usage
for created TLB fence</font>
<div> </div>
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<div class="PlainText">Am 05.09.24 um 10:58 schrieb Dejan
Andjelkovic:<br>
> When using SDMA for PT updates, a TLB fence hooked
to a buffer<br>
> objects dma resv object with usage declared as
BOOKKEEP leaves a<br>
> chance for TLB flush to occur prematurely. This
will lead to a page<br>
> fault. Raising the usage from BOOKKEEP to KERNEL
removes this<br>
> possibility.<br>
<br>
Well that's complete nonsense. The usage model is for
implicit syncing <br>
and not even remotely related to TLB flushing.<br>
<br>
What exactly is the problem you run into?<br>
<br>
Regards,<br>
Christian.<br>
<br>
><br>
> Signed-off-by: Dejan Andjelkovic
<a class="moz-txt-link-rfc2396E" href="mailto:Dejan.Andjelkovic@amd.com"><Dejan.Andjelkovic@amd.com></a><br>
> ---<br>
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +-<br>
> 1 file changed, 1 insertion(+), 1 deletion(-)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c<br>
> index f93804902fd3..8efc2cf9bbb0 100644<br>
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c<br>
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c<br>
> @@ -928,7 +928,7 @@ amdgpu_vm_tlb_flush(struct
amdgpu_vm_update_params *params,<br>
> <br>
> /* Makes sure no PD/PT is freed
before the flush */<br>
>
dma_resv_add_fence(vm->root.bo->tbo.base.resv,
*fence,<br>
> -
DMA_RESV_USAGE_BOOKKEEP);<br>
> +
DMA_RESV_USAGE_KERNEL);<br>
> }<br>
> }<br>
> <br>
<br>
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