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[Public]<br>
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Acked-by: Alex Deucher <alexander.deucher@amd.com></div>
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<div id="divRplyFwdMsg" dir="ltr"><font face="Calibri, sans-serif" style="font-size:11pt" color="#000000"><b>From:</b> Zhu, Lingshan <Lingshan.Zhu@amd.com><br>
<b>Sent:</b> Tuesday, September 24, 2024 11:09 PM<br>
<b>To:</b> Deucher, Alexander <Alexander.Deucher@amd.com><br>
<b>Cc:</b> Huang, Ray <Ray.Huang@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Zhu, Lingshan <Lingshan.Zhu@amd.com>; Du, Bin <Bin.Du@amd.com><br>
<b>Subject:</b> [PATCH 2/2] drm/amdgpu: init saw registers for mmhub v1.0</font>
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<div class="PlainText">This commits init registers in the Stand Along Walker<br>
for mmhub v1.0, to support ISP use cases.<br>
<br>
Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com><br>
Reported-and-Tested-by: Du Bin <bin.du@amd.com><br>
---<br>
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 49 +++++++++++++++++++<br>
.../include/asic_reg/mmhub/mmhub_1_0_offset.h | 23 +++++++++<br>
2 files changed, 72 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c<br>
index e3ddd22aa172..e9a6f33ca710 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c<br>
@@ -229,6 +229,52 @@ static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)<br>
0);<br>
}<br>
<br>
+static void mmhub_v1_0_init_saw(struct amdgpu_device *adev)<br>
+{<br>
+ uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);<br>
+ uint32_t tmp;<br>
+<br>
+ /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 */<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,<br>
+ lower_32_bits(pt_base >> 12));<br>
+<br>
+ /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 */<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,<br>
+ upper_32_bits(pt_base >> 12));<br>
+<br>
+ /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 */<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,<br>
+ (u32)(adev->gmc.gart_start >> 12));<br>
+<br>
+ /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 */<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,<br>
+ (u32)(adev->gmc.gart_start >> 44));<br>
+<br>
+ /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 */<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,<br>
+ (u32)(adev->gmc.gart_end >> 12));<br>
+<br>
+ /* VM_9_X_REGISTER_VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 */<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,<br>
+ (u32)(adev->gmc.gart_end >> 44));<br>
+<br>
+ /* Program SAW CONTEXT0 CNTL */<br>
+ tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL);<br>
+ tmp |= 1 << CONTEXT0_CNTL_ENABLE_OFFSET;<br>
+ tmp &= ~(3 << CONTEXT0_CNTL_PAGE_TABLE_DEPTH_OFFSET);<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXT0_CNTL, tmp);<br>
+<br>
+ /* Disable all Contexts except Context0 */<br>
+ tmp = 0xfffe;<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CONTEXTS_DISABLE, tmp);<br>
+<br>
+ /* Program SAW CNTL4 */<br>
+ tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4);<br>
+ tmp |= 1 << VMC_TAP_PDE_REQUEST_SNOOP_OFFSET;<br>
+ tmp |= 1 << VMC_TAP_PTE_REQUEST_SNOOP_OFFSET;<br>
+ WREG32_SOC15(MMHUB, 0, mmVM_L2_SAW_CNTL4, tmp);<br>
+}<br>
+<br>
static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)<br>
{<br>
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB0(0)];<br>
@@ -283,6 +329,9 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)<br>
i * hub->ctx_addr_distance,<br>
upper_32_bits(adev->vm_manager.max_pfn - 1));<br>
}<br>
+<br>
+ if (amdgpu_ip_version(adev, ISP_HWIP, 0))<br>
+ mmhub_v1_0_init_saw(adev);<br>
}<br>
<br>
static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev)<br>
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h<br>
index 2c3ce243861a..380e44230bda 100644<br>
--- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h<br>
+++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_0_offset.h<br>
@@ -1232,6 +1232,29 @@<br>
#define mmMC_VM_MX_L1_PERFCOUNTER_HI 0x059d<br>
#define mmMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 0<br>
<br>
+// Stand Alone Walker Registers<br>
+#define VMC_TAP_PDE_REQUEST_SNOOP_OFFSET 8<br>
+#define VMC_TAP_PTE_REQUEST_SNOOP_OFFSET 11<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0606<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0607<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0608<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0609<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x060a<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x060b<br>
+#define mmVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0<br>
+#define mmVM_L2_SAW_CONTEXT0_CNTL 0x0604<br>
+#define mmVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 0<br>
+#define CONTEXT0_CNTL_ENABLE_OFFSET 0<br>
+#define CONTEXT0_CNTL_PAGE_TABLE_DEPTH_OFFSET 1<br>
+#define mmVM_L2_SAW_CONTEXTS_DISABLE 0x060c<br>
+#define mmVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 0<br>
+#define mmVM_L2_SAW_CNTL4 0x0603<br>
+#define mmVM_L2_SAW_CNTL4_BASE_IDX 0<br>
<br>
// addressBlock: mmhub_utcl2_atcl2dec<br>
// base address: 0x69900<br>
-- <br>
2.43.5<br>
<br>
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