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[AMD Official Use Only - AMD Internal Distribution Only]<br>
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif">Hi, Christian,
</span> <span style="font-size:11.0pt;font-family:"Arial",sans-serif">Raina, Yera.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif">If this issue in rocm, I need assign my ticket
<a href="https://ontrack-internal.amd.com/browse/SWDEV-459983">SWDEV-459983</a> to rocm team.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif">Is there anything to share with the rocm pm?<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif">Such as the Email or chat history or the ticket you talk with
</span><span class="ui-provider">Andjelkovic.</span><span style="font-size:11.0pt;font-family:"Arial",sans-serif"><o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif">Thanks,<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif">Chong.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Arial",sans-serif"><o:p> </o:p></span></p>
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<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Koenig, Christian <Christian.Koenig@amd.com>
<br>
<b>Sent:</b> Monday, October 21, 2024 4:00 PM<br>
<b>To:</b> Li, Chong(Alan) <Chong.Li@amd.com>; amd-gfx@lists.freedesktop.org<br>
<b>Cc:</b> cao, lin <lin.cao@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amd/amdgpu: change the flush gpu tlb mode to sync mode.<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Am 21.10.24 um 07:56 schrieb Chong Li:<br>
<br>
<o:p></o:p></p>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<pre>change the gpu tlb flush mode to sync mode to<o:p></o:p></pre>
<pre>solve the issue in the rocm stress test.<o:p></o:p></pre>
</blockquote>
<p class="MsoNormal"><br>
And again complete NAK to this.<br>
<br>
I've already proven together with <span class="ui-provider">Andjelkovic that the problem is that the rocm stress test is broken.</span><br>
<br>
<span class="ui-provider">The test tries to access memory before it is probably mapped and that is provable by looking into the tracelogs.</span><br>
<br>
<span class="ui-provider">Regards,</span><br>
<span class="ui-provider">Christian. </span><br>
<br>
<br>
<o:p></o:p></p>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<pre><o:p> </o:p></pre>
<pre><o:p> </o:p></pre>
<pre>Signed-off-by: Chong Li <a href="mailto:chongli2@amd.com"><chongli2@amd.com></a><o:p></o:p></pre>
<pre>---<o:p></o:p></pre>
<pre> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c | 4 ++--<o:p></o:p></pre>
<pre> 1 file changed, 2 insertions(+), 2 deletions(-)<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c<o:p></o:p></pre>
<pre>index 51cddfa3f1e8..4d9ff7b31618 100644<o:p></o:p></pre>
<pre>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c<o:p></o:p></pre>
<pre>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c<o:p></o:p></pre>
<pre>@@ -98,7 +98,6 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm<o:p></o:p></pre>
<pre> f->adev = adev;<o:p></o:p></pre>
<pre> f->dependency = *fence;<o:p></o:p></pre>
<pre> f->pasid = vm->pasid;<o:p></o:p></pre>
<pre>- INIT_WORK(&f->work, amdgpu_tlb_fence_work);<o:p></o:p></pre>
<pre> spin_lock_init(&f->lock);<o:p></o:p></pre>
<pre> <o:p></o:p></pre>
<pre> dma_fence_init(&f->base, &amdgpu_tlb_fence_ops, &f->lock,<o:p></o:p></pre>
<pre>@@ -106,7 +105,8 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm<o:p></o:p></pre>
<pre> <o:p></o:p></pre>
<pre> /* TODO: We probably need a separate wq here */<o:p></o:p></pre>
<pre> dma_fence_get(&f->base);<o:p></o:p></pre>
<pre>- schedule_work(&f->work);<o:p></o:p></pre>
<pre> <o:p></o:p></pre>
<pre> *fence = &f->base;<o:p></o:p></pre>
<pre>+<o:p></o:p></pre>
<pre>+ amdgpu_tlb_fence_work(&f->work);<o:p></o:p></pre>
<pre> }<o:p></o:p></pre>
</blockquote>
<p class="MsoNormal"><o:p> </o:p></p>
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