<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" xmlns="http://www.w3.org/TR/REC-html40"> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta name="Generator" content="Microsoft Word 15 (filtered medium)"> <style></style> </head> <body lang="EN-US" link="blue" vlink="purple" style="word-wrap:break-word"> [AMD Official Use Only - AMD Internal Distribution Only] <div> <div class="WordSection1"> Hi, Christian.<o:p></o:p> <o:p> </o:p> <o:p> </o:p> Share the process of the page fault issue in rocblas benchmark.<o:p></o:p> <o:p> </o:p> Find when there are multithreads read register “regIH_VMID_0_LUT” to get pasid, <o:p></o:p> This register will return error pasid value randomly, sometimes is 0, sometimes is 32768, (the real value is 32770).<o:p></o:p> After check the invalid pasid, code will “continue” and not flush the gpu tlb.<o:p></o:p> <o:p> </o:p> That’s why the page fault accours.<o:p></o:p> <o:p> </o:p> After add the lock, the register not return invalid value, and the rocblas benchmark passed.<o:p></o:p> <o:p> </o:p> You have submit a patch "implement TLB flush fence", in this patch you create a kernel thread to flush gpu tlb.<o:p></o:p> And in main thread the function “svm_range_map_to_gpus” will call function “kfd_flush_tlb” and then flush gpu tlb as well.<o:p></o:p> Means that both the two threads will call function “gmc_v11_0_flush_gpu_tlb_pasid”.<o:p></o:p> So after you merge your patch, the page fault issue accours.<o:p></o:p> <o:p> </o:p> My first patch change flush gpu tlb to sync mode, <o:p></o:p> means the one thread flush the gpu tlb twice, so my first patch passed the rocblas benchmark.<o:p></o:p> <o:p> </o:p> I already submit an email to firmware team to ask why the register will return wrong value.<o:p></o:p> <o:p> </o:p> But if the firmware team not able to solve this issue, or need a long time to solve this issue,<o:p></o:p> I will submit the patch like below to do the workaround.<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <img width="740" height="649" style="width:7.7083in;height:6.7583in" id="_x0000_i1032" src="cid:image008.png@01DB2BBD.60C81420"><o:p></o:p> <o:p> </o:p> <o:p> </o:p> Thanks,<o:p></o:p> Chong.<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Li, Chong(Alan) Sent: Friday, October 25, 2024 2:46 PM To: Koenig, Christian <Christian.Koenig@amd.com>; Andjelkovic, Dejan <Dejan.Andjelkovic@amd.com> Cc: cao, lin <lin.cao@amd.com>; Yin, ZhenGuo (Chris) <ZhenGuo.Yin@amd.com>; Zhang, Tiantian (Celine) <Tiantian.Zhang@amd.com>; amd-gfx@lists.freedesktop.org Subject: RE: [PATCH] drm/amd/amdgpu: change the flush gpu tlb mode to sync mode.<o:p></o:p> </div> </div> <o:p> </o:p> Hi, Christian.<o:p></o:p> <o:p> </o:p> The size of log file so large, can’t paste in the Email.<o:p></o:p> <o:p> </o:p> I copy the log file in directory “<a href="file://ark/incoming/chong/log">\\ark\incoming\chong\log</a>”, the log file name is “kern.log”.<o:p></o:p> <o:p> </o:p> Can you access this directory ?<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> <o:p> </o:p> Thanks,<o:p></o:p> Chong.<o:p></o:p> <o:p> </o:p> <o:p> </o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Koenig, Christian <<a href="mailto:Christian.Koenig@amd.com">Christian.Koenig@amd.com</a>> Sent: Thursday, October 24, 2024 7:22 PM To: Li, Chong(Alan) <<a href="mailto:Chong.Li@amd.com">Chong.Li@amd.com</a>>; Andjelkovic, Dejan <<a href="mailto:Dejan.Andjelkovic@amd.com">Dejan.Andjelkovic@amd.com</a>> Cc: cao, lin <<a href="mailto:lin.cao@amd.com">lin.cao@amd.com</a>>; Yin, ZhenGuo (Chris) <<a href="mailto:ZhenGuo.Yin@amd.com">ZhenGuo.Yin@amd.com</a>>; Zhang, Tiantian (Celine) <<a href="mailto:Tiantian.Zhang@amd.com">Tiantian.Zhang@amd.com</a>>; Raina, Yera <<a href="mailto:Yera.Raina@amd.com">Yera.Raina@amd.com</a>> Subject: Re: [PATCH] drm/amd/amdgpu: change the flush gpu tlb mode to sync mode.<o:p></o:p> </div> </div> <o:p> </o:p> Do you have the full log as text file? As image it's pretty much useless. Regards, Christian.<o:p></o:p> <div> Am 24.10.24 um 09:41 schrieb Li, Chong(Alan):<o:p></o:p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> [AMD Official Use Only - AMD Internal Distribution Only]<o:p></o:p> <o:p> </o:p> <div> Hi, Christian.<o:p></o:p> <o:p></o:p> We can see the dmesg log,<o:p></o:p> After address “7ef90be00” already update the ptes, page fault still happen.<o:p></o:p> <o:p></o:p> <o:p></o:p> <img border="0" width="714" height="260" style="width:7.4333in;height:2.7083in" id="Picture_x0020_7" src="cid:image001.png@01DB2BAC.E798ED50"><o:p></o:p> <o:p></o:p> <img border="0" width="789" height="207" style="width:8.2166in;height:2.1583in" id="Picture_x0020_6" src="cid:image002.png@01DB2BAC.E798ED50"><o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> Thanks,<o:p></o:p> Chong.<o:p></o:p> <o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Koenig, Christian <a href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a> Sent: Wednesday, October 23, 2024 5:26 PM To: Li, Chong(Alan) <a href="mailto:Chong.Li@amd.com"><Chong.Li@amd.com></a>; Andjelkovic, Dejan <a href="mailto:Dejan.Andjelkovic@amd.com"><Dejan.Andjelkovic@amd.com></a> Cc: cao, lin <a href="mailto:lin.cao@amd.com"><lin.cao@amd.com></a>; Yin, ZhenGuo (Chris) <a href="mailto:ZhenGuo.Yin@amd.com"><ZhenGuo.Yin@amd.com></a>; Zhang, Tiantian (Celine) <a href="mailto:Tiantian.Zhang@amd.com"><Tiantian.Zhang@amd.com></a>; Raina, Yera <a href="mailto:Yera.Raina@amd.com"><Yera.Raina@amd.com></a> Subject: Re: [PATCH] drm/amd/amdgpu: change the flush gpu tlb mode to sync mode.<o:p></o:p> </div> </div> <o:p></o:p> Hi Chong, oh that could indeed be. I suggest to add a trace point for the page fault so that we can guarantee that we use the same time basis for both events. That should make it trivial to compare them. Regards, Christian.<o:p></o:p> <div> Am 23.10.24 um 10:17 schrieb Li, Chong(Alan):<o:p></o:p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> [AMD Official Use Only - AMD Internal Distribution Only]<o:p></o:p> <o:p></o:p> <div> Hi, Christian.<o:p></o:p> <o:p></o:p> I add a log in kernel, and prove the timestamp in tracing log is slower than dmesg log, <o:p></o:p> so we can’t give a conclusion that the issue in rocm.<o:p></o:p> <o:p></o:p> <o:p></o:p> ------------------------ the information I sync with Andjelkovic, Dejan ----------------------------------------<o:p></o:p> dmesg shows that the page fault happens address “0x000072e5f4401000” at time “6587.772178”,<o:p></o:p> <o:p></o:p> <img border="0" width="1318" height="119" style="width:13.7333in;height:1.2416in" id="_x0000_i1029" src="cid:image003.png@01DB2BAC.E798ED50"><o:p></o:p> <o:p></o:p> tracing log shows that the function “amdgpu_vm_update_ptes” be called at time “6587.790869”,<o:p></o:p> <img border="0" width="1167" height="24" style="width:12.1583in;height:.25in" id="Picture_x0020_4" src="cid:image004.png@01DB2BAC.E798ED50"><o:p></o:p> ------------------------ the information I sync with Andjelkovic, Dejan ----------------------------------------<o:p></o:p> <o:p></o:p> <o:p></o:p> From the log time stamp, you give a conclusion that “The test tries to access memory before it is probably mapped and that is provable by looking into the tracelogs.”.<o:p></o:p> <o:p></o:p> But after I review the code, the function “amdgpu_vm_ptes_update” be called in function “svm_range_set_attr”, <o:p></o:p> <o:p></o:p> So, after this log in above dmesg print “[ 6587.772136] amdgpu: pasid 0x8002 svms 0x000000008b03ff39 [0x72e5f4400 0x72e5fc3ff] done, r=0”, <o:p></o:p> the function “svm_range_set_attr” will leave, in that time “amdgpu_vm_ptes_update” is already be called, the timestamp is not reasonable.<o:p></o:p> <o:p></o:p> I think maybe the timestamp in tracing log has some delay, and I add a line of log in kernel to verify my guess,<o:p></o:p> <o:p></o:p> <img border="0" width="792" height="98" style="width:8.25in;height:1.0166in" id="Picture_x0020_3" src="cid:image005.png@01DB2BAC.E798ED50"><o:p></o:p> <o:p></o:p> The below is the result:<o:p></o:p> tracing log shows the address “ffffffc00” at time “227.298607”,<o:p></o:p> dmesg log print the address “ffffffc00” at time “226.756137”.<o:p></o:p> <o:p></o:p> <o:p></o:p> traing log:<o:p></o:p> <img border="0" width="1336" height="143" style="width:13.9166in;height:1.4916in" id="Picture_x0020_2" src="cid:image006.png@01DB2BAC.E798ED50"><o:p></o:p> <o:p></o:p> dmesg log:<o:p></o:p> <img border="0" width="957" height="112" style="width:9.9666in;height:1.1666in" id="Picture_x0020_1" src="cid:image007.png@01DB2BAC.E798ED50"><o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> Thanks,<o:p></o:p> Chong.<o:p></o:p> <o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Li, Chong(Alan) Sent: Monday, October 21, 2024 6:38 PM To: Koenig, Christian <a href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a>; Raina, Yera <a href="mailto:Yera.Raina@amd.com"><Yera.Raina@amd.com></a>; Andjelkovic, Dejan <a href="mailto:Dejan.Andjelkovic@amd.com"><Dejan.Andjelkovic@amd.com></a> Cc: cao, lin <a href="mailto:lin.cao@amd.com"><lin.cao@amd.com></a>; Yin, ZhenGuo (Chris) <a href="mailto:ZhenGuo.Yin@amd.com"><ZhenGuo.Yin@amd.com></a>; Zhang, Tiantian (Celine) <a href="mailto:Tiantian.Zhang@amd.com"><Tiantian.Zhang@amd.com></a> Subject: RE: [PATCH] drm/amd/amdgpu: change the flush gpu tlb mode to sync mode.<o:p></o:p> </div> </div> <o:p></o:p> Hi, Christian.<o:p></o:p> Thanks for your reply,<o:p></o:p> And do you have any advice about this issue?<o:p></o:p> <o:p></o:p> <o:p></o:p> Hi, Raina, Year. Share I assign this ticket <a href="https://ontrack-internal.amd.com/browse/SWDEV-459983">SWDEV-459983</a> to rocm team?<o:p></o:p> <o:p></o:p> <o:p></o:p> <o:p></o:p> Thanks,<o:p></o:p> Chong.<o:p></o:p> <o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Koenig, Christian <<a href="mailto:Christian.Koenig@amd.com">Christian.Koenig@amd.com</a>> Sent: Monday, October 21, 2024 6:08 PM To: Li, Chong(Alan) <<a href="mailto:Chong.Li@amd.com">Chong.Li@amd.com</a>>; Raina, Yera <<a href="mailto:Yera.Raina@amd.com">Yera.Raina@amd.com</a>> Cc: cao, lin <<a href="mailto:lin.cao@amd.com">lin.cao@amd.com</a>>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> Subject: Re: [PATCH] drm/amd/amdgpu: change the flush gpu tlb mode to sync mode.<o:p></o:p> </div> </div> <o:p></o:p> Hi Chong, Andjelkovic just shared a bunch of traces from rocm on teams with me which I analyzed. When you know what you look for it's actually pretty obvious what's going on. Just look at the timestamp of the fault and compare that with the timestamp of the operation mapping something at the given address. When mapping an address happens only after accessing an address then there is clearly something wrong in the code which coordinates this and that is the ROCm stress test tool in this case. Regards, Christian.<o:p></o:p> <div> Am 21.10.24 um 11:02 schrieb Li, Chong(Alan):<o:p></o:p> </div> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> [AMD Official Use Only - AMD Internal Distribution Only]<o:p></o:p> <o:p></o:p> <div> Hi, Christian, Raina, Yera.<o:p></o:p> <o:p></o:p> If this issue in rocm, I need assign my ticket <a href="https://ontrack-internal.amd.com/browse/SWDEV-459983">SWDEV-459983</a> to rocm team.<o:p></o:p> <o:p></o:p> Is there anything to share with the rocm pm?<o:p></o:p> Such as the Email or chat history or the ticket you talk with Andjelkovic.<o:p></o:p> <o:p></o:p> Thanks,<o:p></o:p> Chong.<o:p></o:p> <o:p></o:p> <div> <div style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in"> From: Koenig, Christian <a href="mailto:Christian.Koenig@amd.com"><Christian.Koenig@amd.com></a> Sent: Monday, October 21, 2024 4:00 PM To: Li, Chong(Alan) <a href="mailto:Chong.Li@amd.com"><Chong.Li@amd.com></a>; <a href="mailto:amd-gfx@lists.freedesktop.org">amd-gfx@lists.freedesktop.org</a> Cc: cao, lin <a href="mailto:lin.cao@amd.com"><lin.cao@amd.com></a> Subject: Re: [PATCH] drm/amd/amdgpu: change the flush gpu tlb mode to sync mode.<o:p></o:p> </div> </div> <o:p></o:p> Am 21.10.24 um 07:56 schrieb Chong Li: <o:p></o:p> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <pre>change the gpu tlb flush mode to sync mode to<o:p></o:p></pre> <pre>solve the issue in the rocm stress test.<o:p></o:p></pre> </blockquote> And again complete NAK to this. I've already proven together with Andjelkovic that the problem is that the rocm stress test is broken. The test tries to access memory before it is probably mapped and that is provable by looking into the tracelogs. Regards, Christian. <o:p></o:p> <blockquote style="margin-top:5.0pt;margin-bottom:5.0pt"> <pre> <o:p></o:p></pre> <pre> <o:p></o:p></pre> <pre>Signed-off-by: Chong Li <a href="mailto:chongli2@amd.com"><chongli2@amd.com></a><o:p></o:p></pre> <pre>---<o:p></o:p></pre> <pre> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c | 4 ++--<o:p></o:p></pre> <pre> 1 file changed, 2 insertions(+), 2 deletions(-)<o:p></o:p></pre> <pre> <o:p></o:p></pre> <pre>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c<o:p></o:p></pre> <pre>index 51cddfa3f1e8..4d9ff7b31618 100644<o:p></o:p></pre> <pre>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c<o:p></o:p></pre> <pre>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c<o:p></o:p></pre> <pre>@@ -98,7 +98,6 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm<o:p></o:p></pre> <pre> f->adev = adev;<o:p></o:p></pre> <pre> f->dependency = *fence;<o:p></o:p></pre> <pre> f->pasid = vm->pasid;<o:p></o:p></pre> <pre>- INIT_WORK(&f->work, amdgpu_tlb_fence_work);<o:p></o:p></pre> <pre> spin_lock_init(&f->lock);<o:p></o:p></pre> <pre> <o:p></o:p></pre> <pre> dma_fence_init(&f->base, &amdgpu_tlb_fence_ops, &f->lock,<o:p></o:p></pre> <pre>@@ -106,7 +105,8 @@ void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm<o:p></o:p></pre> <pre> <o:p></o:p></pre> <pre> /* TODO: We probably need a separate wq here */<o:p></o:p></pre> <pre> dma_fence_get(&f->base);<o:p></o:p></pre> <pre>- schedule_work(&f->work);<o:p></o:p></pre> <pre> <o:p></o:p></pre> <pre> *fence = &f->base;<o:p></o:p></pre> <pre>+<o:p></o:p></pre> <pre>+ amdgpu_tlb_fence_work(&f->work);<o:p></o:p></pre> <pre> }<o:p></o:p></pre> </blockquote> <o:p></o:p> </div> </blockquote> <o:p></o:p> </div> </blockquote> <o:p></o:p> </div> </blockquote> <o:p> </o:p> </div> </div> </body> </html>