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[AMD Official Use Only - AMD Internal Distribution Only]<br>
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Hi Lijo,</div>
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This will not affect 1VF mode. I just matched SMU supported/unsupported VF msg . </div>
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Messages for 1 VF mode are still enabled, such as handle smu features, handle soft frequences, etc.</div>
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<p>Thanks.</p>
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<p>Best regard,</p>
<p>Yifan Zha</p>
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<div dir="ltr" id="divRplyFwdMsg"><span style="font-family: Calibri, sans-serif; font-size: 11pt; color: rgb(0, 0, 0);"><b>From:</b> Lazar, Lijo <Lijo.Lazar@amd.com><br>
<b>Sent:</b> Tuesday, January 21, 2025 5:48 PM<br>
<b>To:</b> Zha, YiFan(Even) <Yifan.Zha@amd.com>; amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com><br>
<b>Cc:</b> Chen, Horace <Horace.Chen@amd.com>; Chang, HaiJun <HaiJun.Chang@amd.com><br>
<b>Subject:</b> Re: [PATCH] drm/amd/pm: Update smu_v13_0_0 SRIOV VF flag in msg mapping table</span>
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On 1/20/2025 9:19 AM, Yifan Zha wrote:<br>
> [Why]<br>
> Under SRIOV VF, driver send a VF unsupportted smu message causing<br>
> a failure.<br>
><br>
> [How]<br>
> Update smu_v13_0_0 message mapping table based on PMFW.<br>
><br>
<br>
Does this hold good for 1VF case also?<br>
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Thanks,<br>
Lijo<br>
<br>
> Signed-off-by: Yifan Zha <Yifan.Zha@amd.com><br>
> ---<br>
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 +++---<br>
> 1 file changed, 3 insertions(+), 3 deletions(-)<br>
><br>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c<br>
> index 0551a3311217..985355bf78b2 100644<br>
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c<br>
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c<br>
> @@ -126,7 +126,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =<br>
> MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),<br>
> MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),<br>
> MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),<br>
> - MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),<br>
> + MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0),<br>
> MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),<br>
> MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),<br>
> MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),<br>
> @@ -140,7 +140,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =<br>
> MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),<br>
> MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),<br>
> MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),<br>
> - MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),<br>
> + MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),<br>
> MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),<br>
> MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),<br>
> MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),<br>
> @@ -149,7 +149,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =<br>
> MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),<br>
> MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),<br>
> MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),<br>
> - MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),<br>
> + MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 0),<br>
> MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),<br>
> MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),<br>
> MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),<br>
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