<div dir="ltr"><div>This is not in device_info, but it'll do.</div><div><br></div><div>Reviewed-by: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>></div><div><br></div><div>Marek</div></div><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">On Mon, Mar 17, 2025 at 5:38 PM Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Add an INFO query to check if user queues are supported.<br>
<br>
v2: switch to a mask of IPs (Marek)<br>
<br>
Cc: <a href="mailto:marek.olsak@amd.com" target="_blank">marek.olsak@amd.com</a><br>
Cc: <a href="mailto:prike.liang@amd.com" target="_blank">prike.liang@amd.com</a><br>
Cc: <a href="mailto:sunil.khatri@amd.com" target="_blank">sunil.khatri@amd.com</a><br>
Signed-off-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com" target="_blank">alexander.deucher@amd.com</a>><br>
---<br>
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 13 +++++++++++++<br>
 include/uapi/drm/amdgpu_drm.h           |  8 ++++++++<br>
 2 files changed, 21 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
index 3b7dfd56ccd0e..1d683c0487697 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c<br>
@@ -1340,6 +1340,19 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)<br>
                        return -EINVAL;<br>
                }<br>
        }<br>
+       case AMDGPU_INFO_UQ_SUPPORTED: {<br>
+               struct drm_amdgpu_info_uq_supported uq_supported = {};<br>
+<br>
+               if (adev->userq_funcs[AMDGPU_HW_IP_GFX])<br>
+                       uq_supported.supported |= (1 << AMDGPU_HW_IP_GFX);<br>
+               if (adev->userq_funcs[AMDGPU_HW_IP_COMPUTE])<br>
+                       uq_supported.supported |= (1 << AMDGPU_HW_IP_COMPUTE);<br>
+               if (adev->userq_funcs[AMDGPU_HW_IP_DMA])<br>
+                       uq_supported.supported |= (1 << AMDGPU_HW_IP_DMA);<br>
+               ret = copy_to_user(out, &uq_supported,<br>
+                                  min((size_t)size, sizeof(uq_supported))) ? -EFAULT : 0;<br>
+               return 0;<br>
+       }<br>
        default:<br>
                DRM_DEBUG_KMS("Invalid request %d\n", info->query);<br>
                return -EINVAL;<br>
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h<br>
index 5dbd9037afe75..4b64e91002c05 100644<br>
--- a/include/uapi/drm/amdgpu_drm.h<br>
+++ b/include/uapi/drm/amdgpu_drm.h<br>
@@ -1195,6 +1195,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow {<br>
 #define AMDGPU_INFO_GPUVM_FAULT                        0x23<br>
 /* query FW object size and alignment */<br>
 #define AMDGPU_INFO_UQ_FW_AREAS                        0x24<br>
+/* query if user queues are supported */<br>
+#define AMDGPU_INFO_UQ_SUPPORTED               0x25<br>
<br>
 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0<br>
 #define AMDGPU_INFO_MMR_SE_INDEX_MASK  0xff<br>
@@ -1572,6 +1574,12 @@ struct drm_amdgpu_info_uq_metadata {<br>
        };<br>
 };<br>
<br>
+struct drm_amdgpu_info_uq_supported {<br>
+       /** returns a mask for each IP type (1 << AMDGPU_HW_IP_*) */<br>
+       __u32   supported;<br>
+       __u32   pad;<br>
+};<br>
+<br>
 /*<br>
  * Supported GPU families<br>
  */<br>
-- <br>
2.48.1<br>
<br>
</blockquote></div>